Alternatives and similar repositories for iob-soc-opencryptolinux

Users that are interested in iob-soc-opencryptolinux are comparing it to the libraries listed below

• IObundle / py2hwsw
  a Python framework for managing embedded HW/SW projects
  ☆16Updated this week
• IObundle / iob-soc-opencryptohw
  Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores
  ☆11Updated 3 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• IObundle / iob-versat
  Coarse Grained Reconfigurable Array
  ☆19Updated 4 months ago
• IObundle / iob-eth
  Basic Verilog Ethernet core and C driver functions
  ☆11Updated 3 months ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆44Updated 10 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆21Updated 10 months ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆20Updated 6 months ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 3 weeks ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 4 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆49Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆55Updated last year
• HunterBitos / Implementation-of-AMBA-AXI3-protocol
  Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…
  ☆14Updated 7 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• oprecomp / DDR4_controller
  ☆58Updated 4 years ago
• pulp-platform / axi_llc
  ☆29Updated last month
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago