Running Linux on IOb-SoC-OpenCryptoHW
☆15Aug 15, 2024Updated last year
Alternatives and similar repositories for iob-soc-opencryptolinux
Users that are interested in iob-soc-opencryptolinux are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- a Python framework for managing embedded HW/SW projects☆21Updated this week
- Coarse Grained Reconfigurable Array Generator☆20Jun 8, 2026Updated last week
- RISC-V System on Chip Template☆163May 21, 2026Updated 3 weeks ago
- Verilog Configurable Cache☆200Jun 8, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- UART 16550 core☆40Jul 17, 2014Updated 11 years ago
- A Z80 CPU implemented in Chisel.☆11Sep 20, 2020Updated 5 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Hoddarla is an OS project in Golang targeting RISC-V 64-bit system.☆12Oct 28, 2021Updated 4 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Jun 8, 2026Updated last week
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Jan 30, 2024Updated 2 years ago
- Linux development repository for socfpga☆16May 27, 2026Updated 2 weeks ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Ethernet MAC 10/100 Mbps☆87Oct 2, 2019Updated 6 years ago
- Simple Tool Caller for llama.cpp☆11Aug 12, 2024Updated last year
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- WebUSB FTDI Driver☆28Apr 8, 2023Updated 3 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆235Aug 25, 2020Updated 5 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库!☆18May 9, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga☆15Mar 9, 2025Updated last year
- Dual RISC-V DISC with integrated eFPGA☆18Oct 9, 2021Updated 4 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆18Nov 15, 2022Updated 3 years ago
- ☆20Mar 3, 2026Updated 3 months ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Oct 18, 2018Updated 7 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- Go package to minify JavaScript, which is a direct port of Douglas Crockford's JSMin☆21Nov 4, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆16Dec 14, 2021Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆12May 29, 2026Updated 2 weeks ago
- Side Channel Attack: Differential Power Analysis (DPA) on AES encryption algorithm to deduce secret keys☆12Mar 5, 2018Updated 8 years ago
- ☆18Jan 15, 2026Updated 4 months ago
- ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.☆20May 18, 2026Updated 3 weeks ago