Running Linux on IOb-SoC-OpenCryptoHW
☆16Aug 15, 2024Updated 2 years ago
Alternatives and similar repositories for iob-soc-opencryptolinux
Users that are interested in iob-soc-opencryptolinux are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- Coarse Grained Reconfigurable Array Generator☆22Sep 16, 2026Updated last month
- a Python framework for managing embedded HW/SW projects☆24Oct 14, 2026Updated 2 weeks ago
- RISC-V System on Chip Template☆162Aug 26, 2026Updated 2 months ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Sep 21, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog Configurable Cache☆197Sep 21, 2026Updated last month
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year
- UART 16550 core☆45Jul 17, 2014Updated 12 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆24Oct 1, 2022Updated 4 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- A Z80 CPU implemented in Chisel.☆11Sep 20, 2020Updated 6 years ago
- ☆10Oct 8, 2021Updated 5 years ago
- Hoddarla is an OS project in Golang targeting RISC-V 64-bit system.☆12Oct 28, 2021Updated 5 years ago
- Fast, feature-rich, RISC-V RVA22/RVA23 SoC emulator; runs Ubuntu etc. and more☆15Oct 20, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 5 years ago
- FPGA Many-core Processor Implementation☆11Nov 27, 2024Updated last year
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 15 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Updated this week
- Single Cycle CPU using the RV32I Base Instruction set☆25Nov 5, 2025Updated 11 months ago
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆15Jan 30, 2024Updated 2 years ago
- Linux development repository for socfpga☆17May 27, 2026Updated 5 months ago
- ☆12Jul 6, 2023Updated 3 years ago
- Ibex RISC-V core extended with hardware acceleration of cryptography functions☆14May 10, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs☆28Updated this week
- RISC-V compliant Timer IP☆14May 10, 2024Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- UM-SJTU JI VE450 2021 Summer Capstone Design Project☆10Aug 4, 2021Updated 5 years ago
- ☆12Aug 1, 2023Updated 3 years ago
- Unpack rap.bin back into individual PS3 rap files☆11Nov 23, 2024Updated last year
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆25Jan 7, 2016Updated 10 years ago
- A web-based graphical simulator of a simple 32-bit, single-cycle implementation of RISC-V☆30Mar 16, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Computer Architecture Simulator for RISC-V and TOY☆14Aug 12, 2025Updated last year
- Package provides javascript implementation of algorithms that generate various types of splines from a set of control way points☆15May 30, 2017Updated 9 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆12Jul 28, 2019Updated 7 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Oct 18, 2018Updated 8 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- Verilog PreProcessor.☆12Nov 9, 2015Updated 10 years ago
- 路科验证V0实验，完成一个router设计的验证工作☆11Jun 10, 2021Updated 5 years ago