XS-MLVP / env-xs-ov-00-bpuLinks
香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境
☆29Updated 11 months ago
Alternatives and similar repositories for env-xs-ov-00-bpu
Users that are interested in env-xs-ov-00-bpu are comparing it to the libraries listed below
Sorting:
- ☆82Updated 5 months ago
- Pick your favorite language to verify your chip.☆68Updated last week
- Documentation for XiangShan Design☆31Updated last week
- ☆86Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆208Updated 3 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆180Updated 11 months ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆42Updated last week
- Modern co-simulation framework for RISC-V CPUs☆156Updated this week
- ☆67Updated 7 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆52Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 5 months ago
- A framework for building hardware verification platform using software method☆28Updated 2 weeks ago
- ☆206Updated 5 months ago
- ☆67Updated last year
- ☆101Updated this week
- Collect some IC textbooks for learning.☆164Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 4 months ago
- ☆195Updated 2 months ago
- A Study of the SiFive Inclusive L2 Cache☆67Updated last year
- ☆70Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆210Updated last month
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated this week
- ☆53Updated 2 weeks ago
- Run rocket-chip on FPGA☆76Updated last week
- Open-source high-performance RISC-V processor☆28Updated 3 months ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 2 years ago
- XiangShan Frontend Develop Environment☆66Updated this week
- ☆156Updated last week
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago