香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境
☆30Oct 20, 2024Updated last year
Alternatives and similar repositories for env-xs-ov-00-bpu
Users that are interested in env-xs-ov-00-bpu are comparing it to the libraries listed below
Sorting:
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 3 months ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Feb 25, 2026Updated 3 weeks ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 3 months ago
- A word hashing method based on vectors of letter n-grams. Currently transforms text into sequences of numbers.☆10Feb 27, 2018Updated 8 years ago
- ☆28Mar 31, 2025Updated 11 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago
- A framework for building hardware verification platform using software method☆33Dec 24, 2025Updated 2 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated 9 months ago
- ☆12Sep 18, 2024Updated last year
- ☆12Jan 21, 2026Updated last month
- ☆11Dec 23, 2025Updated 2 months ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- ☆14Sep 9, 2020Updated 5 years ago
- ☆43Oct 7, 2023Updated 2 years ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated last month
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆16Apr 12, 2024Updated last year
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated last month
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- ☆15Dec 3, 2020Updated 5 years ago
- ☆14Nov 8, 2023Updated 2 years ago
- 国科大软件安全原理作业☆25Oct 27, 2020Updated 5 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆33Aug 22, 2024Updated last year
- ☆76Mar 7, 2026Updated last week
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- ☆13Feb 14, 2026Updated last month
- syn script for DC Compiler☆14May 15, 2022Updated 3 years ago
- ☆24Jan 8, 2026Updated 2 months ago
- Recent papers related to hardware formal verification.☆77Sep 20, 2023Updated 2 years ago
- A template project for beginning new Chisel work☆694Feb 24, 2026Updated 3 weeks ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Nov 11, 2025Updated 4 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- ☆14Mar 28, 2020Updated 5 years ago