Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
☆17Oct 9, 2021Updated 4 years ago
Alternatives and similar repositories for Pythia-HDL
Users that are interested in Pythia-HDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (ht…☆160Feb 21, 2026Updated 2 months ago
- About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.☆14Mar 1, 2023Updated 3 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆24Jun 30, 2024Updated last year
- Releasing open-sourced version of the code used in the paper "Perceptron-based Prefetch Filtering (ISCA 2019)"☆10May 27, 2022Updated 3 years ago
- ☆19Jan 2, 2026Updated 4 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆10Dec 28, 2020Updated 5 years ago
- Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.☆10Jan 11, 2021Updated 5 years ago
- ☆20Dec 27, 2024Updated last year
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆20Apr 14, 2026Updated 3 weeks ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆18May 17, 2020Updated 5 years ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆14Apr 28, 2026Updated last week
- The source code of "Bingo Spatial Data Prefetcher" paper, which is accepted in HPCA 2019.☆31Jul 29, 2021Updated 4 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆77Feb 21, 2026Updated 2 months ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- MICRO 2024 Evaluation Artifact for FuseMax☆17Aug 26, 2024Updated last year
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- ☆29Mar 31, 2025Updated last year
- ☆10Updated this week
- Source code for the Base-Delta-Immediate Compression Algorithm (described in the PACT 2012 paper by Pekhimenko et al. at http://users.ece…☆28Mar 1, 2015Updated 11 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆44May 29, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Instruction Pointer Classifier and Dynamic Degree Stream based Hardware Cache Prefetching☆16Nov 16, 2019Updated 6 years ago
- ☆18Jul 12, 2024Updated last year
- Parametrized RTL benchmark suite☆26Feb 6, 2026Updated 3 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- ☆141Apr 30, 2026Updated last week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆29May 4, 2025Updated last year
- ☆25Jun 23, 2024Updated last year
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 4 months ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year