A tool to convert Verilog RTL file generated from Xilinx Vivado HLS to an equivalent C Code.
☆12Jun 16, 2021Updated 5 years ago
Alternatives and similar repositories for FastSim
Users that are interested in FastSim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 9 years ago
- A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.☆13Jul 24, 2026Updated 2 months ago
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated 2 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- Official code for DeepGate4☆16Jun 25, 2026Updated 3 months ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 6 years ago
- Power grid analysis☆23Aug 5, 2020Updated 6 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆58Sep 25, 2026Updated 3 weeks ago
- ☆12Jul 20, 2022Updated 4 years ago
- Python version of tools to work with AIG formatted files☆13Sep 7, 2026Updated last month
- ThermalGCN☆10Jan 27, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 5 years ago
- ☆30Oct 4, 2017Updated 9 years ago
- ☆13Jul 3, 2020Updated 6 years ago
- (Model-based) Automated Software Engineering☆10Jun 11, 2017Updated 9 years ago
- ☆10May 22, 2024Updated 2 years ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- ☆19May 24, 2023Updated 3 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆21Dec 10, 2024Updated last year
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆14Aug 5, 2023Updated 3 years ago
- ☆11Updated this week
- A Tensorflow implementation of Stacked Hourglass Network for Keypoint Detection, with several residual layers and can be trained to detec…☆15May 26, 2021Updated 5 years ago
- 🚀 Leveraging advanced RNN with LSTM for efficient, real-time anomaly detection in IoT networks, optimized for performance in resource-co…☆15Nov 25, 2023Updated 2 years ago
- ☆13Jun 23, 2022Updated 4 years ago
- ☆10Sep 14, 2019Updated 7 years ago
- GNN-RE datasets for circuit recognition☆63May 16, 2023Updated 3 years ago
- DeepGate3 for ICCAD2024☆14May 26, 2025Updated last year
- ☆42Sep 19, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- New batched algorithm for sparse matrix-matrix multiplication (SpMM)☆16May 7, 2019Updated 7 years ago
- This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.☆18Apr 25, 2020Updated 6 years ago
- ☆14Jul 16, 2024Updated 2 years ago
- ☆12Oct 2, 2023Updated 3 years ago
- ☆18Mar 7, 2019Updated 7 years ago
- Code for paper 'ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection'☆17Jul 4, 2025Updated last year
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆17Sep 3, 2025Updated last year