Alternatives and similar repositories for hw2vec

Users that are interested in hw2vec are comparing it to the libraries listed below

• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆29Updated 3 years ago
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆55Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆27Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆54Updated 5 months ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆13Updated 2 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 5 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆65Updated 2 weeks ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆62Updated last year
• shalan / AD_SAR_ADC
  Digital Standard Cells based SAR ADC
  ☆14Updated 4 years ago
• Kkalais / Hardware-Trojan-Detection
  Machine Learning Techniques for Hardware Trojan Detection
  ☆28Updated 5 years ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆25Updated 3 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆39Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• ShonTaware / RISC-V_Core_4_Stage
  RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
  ☆15Updated 4 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆125Updated last year
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• cure-lab / DeepGate2
  ☆15Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• IntelLabs / FloorSet
  ☆77Updated 4 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 5 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆53Updated 9 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆68Updated 3 months ago