lilasrahis / GNN4RELLinks
Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 2022
☆20Updated 2 years ago
Alternatives and similar repositories for GNN4REL
Users that are interested in GNN4REL are comparing it to the libraries listed below
Sorting:
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆56Updated 3 months ago
- GNN-RE datasets for circuit recognition☆47Updated 2 years ago
- just checking☆16Updated 2 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆23Updated 3 years ago
- ☆15Updated 2 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- ☆25Updated last year
- Artificial Netlist Generator☆39Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 5 months ago
- ☆43Updated 2 years ago
- Open Circuit Benchmark OCB and source code for CktGNN (https://openreview.net/forum?id=NE2911Kq1sp).☆59Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 10 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆130Updated 8 months ago
- ☆28Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 10 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆22Updated last year
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆14Updated 2 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆45Updated last week
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆10Updated 5 months ago
- ☆12Updated 2 years ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA☆25Updated last month
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆69Updated 3 weeks ago
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆41Updated 2 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆30Updated 10 months ago
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 8 years ago
- ☆29Updated last year
- ☆16Updated 4 years ago
- ☆31Updated 3 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year