SiciliaLeco / hls_cnn_acceleratorLinks
A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.
☆12Updated 4 years ago
Alternatives and similar repositories for hls_cnn_accelerator
Users that are interested in hls_cnn_accelerator are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆163Updated this week
- Chinese Guide for Alveo Getting Started☆12Updated 5 years ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- A list of our chiplet simulaters☆44Updated 5 months ago
- ☆73Updated 10 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆70Updated 4 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated last year
- ☆20Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- The open-sourced version of BOOM-Explorer☆45Updated 2 years ago
- Vivado HLS study notes, courses, documents.☆12Updated 6 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- ☆61Updated 8 months ago
- ☆50Updated 2 weeks ago
- An integrated CGRA design framework☆91Updated 8 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆106Updated 7 months ago
- ☆12Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago