SiciliaLeco / hls_cnn_accelerator
A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.
☆12Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for hls_cnn_accelerator
- ☆13Updated 3 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020☆7Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- Chinese Guide for Alveo Getting Started☆10Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆32Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆30Updated last month
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆64Updated 11 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆56Updated last year
- ☆11Updated 2 months ago
- view at https://xupsh.github.io/ccc2021/☆24Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- ☆45Updated 8 months ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- ☆60Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆16Updated 7 months ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 2 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆22Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- A general framework for optimizing DNN dataflow on systolic array☆33Updated 3 years ago
- ☆11Updated 7 months ago
- An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation☆40Updated 8 months ago
- CamJ: an energy modeling and system-level exploration framework for in-sensor visual computing☆22Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆19Updated 2 weeks ago
- ☆60Updated this week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆10Updated 3 months ago