SiciliaLeco / hls_cnn_accelerator
A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.
☆12Updated 3 years ago
Alternatives and similar repositories for hls_cnn_accelerator:
Users that are interested in hls_cnn_accelerator are comparing it to the libraries listed below
- 关于移植模型至gemmini的文档☆21Updated 2 years ago
- ☆20Updated 5 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆17Updated 7 months ago
- The open-sourced version of BOOM-Explorer☆36Updated last year
- ☆25Updated last month
- RTL generator for SpGEMM☆9Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆25Updated last week
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆57Updated this week
- ☆20Updated last month
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆66Updated 5 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆19Updated 2 years ago
- A co-design architecture on sparse attention☆49Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 4 months ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- ☆24Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆47Updated this week
- ☆21Updated last month
- Implementing the Precise Runahead (HPCA'20) in gem5☆11Updated last year
- ☆22Updated 2 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆23Updated last year
- An HLS based winograd systolic CNN accelerator☆49Updated 3 years ago
- ☆12Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 6 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated last month
- ☆47Updated 11 months ago