Alternatives and similar repositories for hls_cnn_accelerator

Users that are interested in hls_cnn_accelerator are comparing it to the libraries listed below

• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆86Updated 5 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆45Updated 2 years ago
• scalesim-project / scale-sim-v3
  ☆56Updated 2 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• groupsada / DeepBurning
  Automatic generation of FPGA-based learning accelerators for the neural network family
  ☆68Updated 6 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆48Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆82Updated 10 months ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆93Updated 3 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆74Updated 3 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• Inference-and-Optimization / High-Level-Synthesis-Study-Notes
  Vivado HLS study notes, courses, documents.
  ☆12Updated 6 years ago
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆23Updated last year
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆56Updated 2 years ago
• UCLA-VAST / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
  ☆177Updated 5 months ago
• lsq314 / SpMM_TCAD
  ☆20Updated last year
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆108Updated 9 months ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• kabazoka / ViT-Accelerator
  （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.
  ☆20Updated last year
• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆85Updated 9 months ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆22Updated 10 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 6 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆47Updated 7 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆54Updated 7 months ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆33Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆162Updated this week
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆18Updated last year