parasjaing7 / avsdpll_3v3Links
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
☆15Updated 3 years ago
Alternatives and similar repositories for avsdpll_3v3
Users that are interested in avsdpll_3v3 are comparing it to the libraries listed below
Sorting:
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- SRAM☆22Updated 4 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆12Updated 3 years ago
- Python Tool for UVM Testbench Generation☆53Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆61Updated 2 weeks ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- ☆22Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Open Analog Design Environment☆24Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆58Updated 2 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- UART models for cocotb☆29Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 2 months ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 4 years ago