parasjaing7 / avsdpll_3v3View external linksLinks
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
☆15Oct 18, 2021Updated 4 years ago
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