parasjaing7 / avsdpll_3v3Links
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
☆15Updated 3 years ago
Alternatives and similar repositories for avsdpll_3v3
Users that are interested in avsdpll_3v3 are comparing it to the libraries listed below
Sorting:
- ☆42Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- SRAM☆22Updated 5 years ago
- ☆12Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- ☆20Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- This project has files needed to design and characterise flipflop☆20Updated 6 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 9 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated 3 weeks ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆49Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆13Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- A simple DDR3 memory controller☆59Updated 2 years ago