Alternatives and similar repositories for discretize:

Users that are interested in discretize are comparing it to the libraries listed below

• the6p4c / catgirltogds
  converts catgirls to gds files
  ☆15Updated 3 years ago
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 5 months ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆38Updated this week
• whitequark / thunderscope-rs
  ☆13Updated 5 months ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• bad-alloc-heavy-industries / Trawler
  Bulk scrape and download datasheets from various vendors (insult)
  ☆14Updated 3 years ago
• amaranth-lang / playground
  Playground for experimenting with and sharing short Amaranth programs on the web
  ☆14Updated 2 months ago
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆12Updated last month
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• shrine-maiden-heavy-industries / torii-hdl
  A modern hardware definition language and toolchain based on Python
  ☆16Updated 2 weeks ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 4 months ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• charlottia / hdx
  HDL development environment on Nix.
  ☆25Updated 4 months ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆39Updated 2 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated 2 years ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆26Updated last week
• gatecat / subprime
  ☆16Updated 3 years ago
• djg / verilated-rs
  Verilator Porcelain
  ☆47Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆33Updated 4 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆23Updated 3 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆59Updated this week
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆69Updated this week
• stefanpie / sa-placer
  ☆14Updated last year
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆41Updated this week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago