Alternatives and similar repositories for lakeroad

Users that are interested in lakeroad are comparing it to the libraries listed below

• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆11Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆15Updated 7 months ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last year
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆55Updated 2 weeks ago
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• iscas-tis / CHA
  ☆19Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆79Updated last week
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆105Updated this week
• cucapra / patronus
  work in progress, playing around with btor2 in rust
  ☆11Updated 3 weeks ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• David-Durst / embeddedHaskellAetherling
  ☆26Updated 2 years ago
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆22Updated 2 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated last week
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 2 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• gussmith23 / churchroad
  FPGA synthesis tool powered by equality saturation and program synthesis.
  ☆12Updated last week
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆26Updated 2 months ago
• sgpthomas / comp-gen
  Automatically generate a compiler using equality saturation
  ☆30Updated last year
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆29Updated 5 months ago
• euphoric-hardware / rtl-simulation-reading
  ☆17Updated 3 weeks ago