Alternatives and similar repositories for lakeroad

Users that are interested in lakeroad are comparing it to the libraries listed below

• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated 2 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆97Updated last week
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last week
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆36Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• iscas-tis / CHA
  ☆19Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆148Updated last month
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆35Updated 2 weeks ago
• ymanerka / rtlcheck
  RTLCheck
  ☆25Updated 7 years ago
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆23Updated 3 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆20Updated 5 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆57Updated this week
• rdaly525 / coreir
  ☆104Updated 3 years ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆45Updated 10 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆55Updated 3 weeks ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆86Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• David-Durst / embeddedHaskellAetherling
  ☆30Updated 3 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆31Updated 3 years ago