FPGA synthesis tool powered by program synthesis
☆55Dec 15, 2025Updated 3 months ago
Alternatives and similar repositories for lakeroad
Users that are interested in lakeroad are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- egraph on top of sqlite☆13Mar 8, 2022Updated 4 years ago
- egraph <-> json☆16Dec 29, 2025Updated 2 months ago
- Equivalent and redundant mutant detection with e-graphs!!!☆13Jun 14, 2023Updated 2 years ago
- Race Condition Running☆11Updated this week
- Verilog AST☆20Dec 2, 2023Updated 2 years ago
- ☆40Sep 17, 2021Updated 4 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆74May 30, 2025Updated 9 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- Rewrite Rule Inference Using Equality Saturation☆153Jun 6, 2025Updated 9 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119May 14, 2025Updated 10 months ago
- Automatically generate a compiler using equality saturation☆34Apr 3, 2024Updated last year
- Interactive visualizer for e-graphs☆28Jan 13, 2026Updated 2 months ago
- Python bindings for egg☆50Jan 17, 2023Updated 3 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- A Python library for working with logic networks, synthesis, and optimization.☆74Updated this week
- Problems and Results of IWLS 2023 Programming Contest☆17Apr 12, 2025Updated 11 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- Search-based compiler for high-performance DSP programming☆71Oct 29, 2024Updated last year
- A simple package to format Backus-Naur form☆15Feb 9, 2026Updated last month
- GPTQ inference TVM kernel☆40Apr 25, 2024Updated last year
- ☆12Jun 13, 2023Updated 2 years ago
- ☆17Oct 17, 2025Updated 5 months ago
- ☆13Updated this week
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated 8 months ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- Szalinski: A Tool for Synthesizing Structured CAD Models with Equality Saturation and Inverse Transformations☆55Sep 1, 2025Updated 6 months ago
- Logic circuit analysis and optimization☆46Feb 2, 2026Updated last month
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 11 months ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆24Feb 24, 2026Updated last month
- Cyclic theorem prover for equalitional reasoning using egraphs☆27Oct 24, 2023Updated 2 years ago
- A toy compiler for NumPy array expressions that uses e-graphs and MLIR☆118Aug 11, 2025Updated 7 months ago
- ☆15Oct 21, 2020Updated 5 years ago
- ☆16Jan 25, 2026Updated last month
- ☆15Mar 15, 2026Updated last week
- Using e-graphs for logic synthesis (ICCAD'25)☆33Updated this week
- A Hardware Pipeline Description Language☆58Jul 12, 2025Updated 8 months ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆14Apr 12, 2023Updated 2 years ago