gussmith23 / lakeroad
FPGA synthesis tool powered by program synthesis
☆37Updated last month
Alternatives and similar repositories for lakeroad:
Users that are interested in lakeroad are comparing it to the libraries listed below
- compiling DSLs to high-level hardware instructions☆22Updated 2 years ago
- BTOR2 MLIR project☆20Updated last year
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- Automatically generate a compiler using equality saturation☆27Updated 9 months ago
- ☆40Updated 3 years ago
- A translation validation framework for MLIR☆78Updated 2 months ago
- ☆16Updated 3 years ago
- Pono: A flexible and extensible SMT-based model checker☆87Updated 2 months ago
- The source code to the Voss II Hardware Verification Suite☆53Updated 4 months ago
- A minimal development of SSA theory☆105Updated this week
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆73Updated 7 months ago
- CoreIR Symbolic Analyzer☆63Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆88Updated 6 months ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆62Updated this week
- A Hardware Pipeline Description Language☆44Updated last year
- Verilog development and verification project for HOL4☆24Updated 2 months ago
- A enumerator for MLIR, relying on the information given by IRDL.☆18Updated 4 months ago
- embedding MLIR in LEAN☆47Updated 7 months ago
- ☆25Updated 2 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 3 years ago
- outline and links for PLDI 2022 tutorial☆17Updated 2 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆26Updated 2 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆10Updated last month
- Time-sensitive affine types for predictable hardware generation☆138Updated 6 months ago
- Website for CS 265☆26Updated 3 weeks ago
- Memory consistency modelling using Alloy☆28Updated 4 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆12Updated 3 years ago
- ☆16Updated 6 months ago
- CHERI-RISC-V model written in Sail☆56Updated last week