Alternatives and similar repositories for SMTAttack

Users that are interested in SMTAttack are comparing it to the libraries listed below

• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 11 months ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆64Updated 5 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆25Updated last year
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆73Updated 2 months ago
• ics-jku / epex-formal-rv32-model
  A RISC-V RV32 model ready for SMT program synthesis.
  ☆12Updated 4 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆110Updated this week
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆56Updated last week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆99Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆111Updated 3 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• antmicro / rowhammer-tester
  ☆64Updated 3 months ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆137Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated last month
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆88Updated last year
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆19Updated 2 years ago
• ucb-bar / sha3
  ☆81Updated last year
• CommonEvaluationPlatform / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…
  ☆23Updated 11 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 3 weeks ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆216Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆147Updated this week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated this week
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆109Updated 3 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated last month
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆190Updated this week