Alternatives and similar repositories for icesugar-chisel

Users that are interested in icesugar-chisel are comparing it to the libraries listed below

• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• micro-FPGA / riscv-contest-2018
  RISCV SoftCPU Contest 2018
  ☆14Updated 6 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆50Updated 4 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆45Updated 2 weeks ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆55Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 9 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 7 months ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆30Updated 3 years ago
• BerkeleyLab / XVC-FTDI-JTAG
  Xilinx virtual cable server for generic FTDI 4232H.
  ☆59Updated last year
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆51Updated 3 years ago
• lambdaconcept / lambdasoc
  ☆44Updated 7 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆31Updated last year
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago