ekiwi / icesugar-chiselLinks
Chisel Examples for the iCESugar FPGA Board
☆11Updated 4 years ago
Alternatives and similar repositories for icesugar-chisel
Users that are interested in icesugar-chisel are comparing it to the libraries listed below
Sorting:
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- A configurable USB 2.0 device core☆31Updated 5 years ago
- ☆45Updated 2 years ago
- Spen's Official OpenOCD Mirror☆50Updated 3 months ago
- demo project to show how to use vivado tcl scripts to do everything.☆16Updated 9 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- ☆34Updated 4 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆28Updated 5 months ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated 3 weeks ago
- Small footprint and configurable SPI core☆42Updated last week
- Experimental flows using nextpnr for Xilinx devices☆48Updated 2 weeks ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- sample VCD files☆37Updated last year
- Drive a Wishbone master bus with an SPI bus.☆10Updated 2 months ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Docker Development Environment for SpinalHDL☆20Updated 10 months ago