Alternatives and similar repositories for icesugar-chisel

Users that are interested in icesugar-chisel are comparing it to the libraries listed below

• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 4 months ago
• micro-FPGA / riscv-contest-2018
  RISCV SoftCPU Contest 2018
  ☆14Updated 6 years ago
• BerkeleyLab / XVC-FTDI-JTAG
  Xilinx virtual cable server for generic FTDI 4232H.
  ☆58Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆97Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated this week
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆38Updated 3 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆89Updated 6 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆84Updated last month
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆82Updated last year
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆92Updated 5 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆42Updated 2 weeks ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆65Updated last week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆66Updated 5 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last month
• olofk / observer
  ☆41Updated 5 years ago
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago