Chisel Examples for the iCESugar FPGA Board
☆12May 4, 2021Updated 4 years ago
Alternatives and similar repositories for icesugar-chisel
Users that are interested in icesugar-chisel are comparing it to the libraries listed below
Sorting:
- Hardware Description from Technical Documentation☆14Jan 12, 2026Updated last month
- Python curses-based tool for configuring STM32 pins.☆15Apr 1, 2022Updated 3 years ago
- Layout, rendering ELK Graph generated by easysoc-firrtl, and display the graph as an interactive diagram to represent Chisel generated Fi…☆12Apr 1, 2022Updated 3 years ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- ☆28Nov 15, 2019Updated 6 years ago
- ☆30Mar 13, 2025Updated 11 months ago
- ☆35Jun 20, 2023Updated 2 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- ECP5 FPGA in an "S7 Mini" form factor☆89Aug 13, 2021Updated 4 years ago
- ☆31Updated this week
- A fork of OpenOCD with support for STM32G4☆12Nov 29, 2021Updated 4 years ago
- Neural network from scratch in Python using Numpy☆11May 28, 2017Updated 8 years ago
- A simple program to convert gdsII files to vector output formats. Currently used to create laser-cut models of standard cells.☆12May 30, 2023Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Analyze experimental data with Programming by Navigation☆17Feb 24, 2026Updated last week
- PREEMPT_RT Linux for Real-time Edge Software☆13Dec 18, 2025Updated 2 months ago
- USB Full-Speed core written in migen/LiteX☆43Mar 14, 2019Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Mar 16, 2025Updated 11 months ago
- tinyVision.ai Vision & Sensor FPGA System on Module☆46Jun 23, 2021Updated 4 years ago
- ☆44Mar 12, 2025Updated 11 months ago
- IRC bot for announcing commits pushed to a git repository☆21Jan 4, 2016Updated 10 years ago
- ☆11May 21, 2021Updated 4 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- CKLink_Lite☆11Oct 18, 2021Updated 4 years ago
- ☆13Dec 2, 2025Updated 3 months ago
- KiCad Action Plugin to hide all References on a PCB☆12Sep 18, 2024Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- GNU/GCC Toolchains that can be optionally used for real-time-cpp on Windows☆14Dec 22, 2024Updated last year
- ☆22Feb 25, 2026Updated last week
- A Simple As Possible RISCV-32I core with debug module.☆42Dec 1, 2019Updated 6 years ago
- ACI-GetStarted☆11Jun 4, 2025Updated 9 months ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- ☆14Dec 7, 2015Updated 10 years ago
- Port the InfoNES to STM32F429I-DISCO☆11Apr 14, 2016Updated 9 years ago
- ☆12Apr 29, 2023Updated 2 years ago
- ☆18Apr 3, 2016Updated 9 years ago