Alternatives and similar repositories for fstdumper

Users that are interested in fstdumper are comparing it to the libraries listed below

• SpinalHDL / CocotbLib
  ☆16Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆24Updated 3 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 weeks ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• alexander-forster / cohdl
  A Python to VHDL compiler
  ☆16Updated last month
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆23Updated 2 weeks ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆14Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆42Updated last week
• pulp-platform / cheshire-ihp130-o
  ☆44Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• pulp-platform / axi_llc
  ☆29Updated last month
• ics-jku / instruction-decoder
  ☆11Updated this week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• avidan-efody / pyreg
  Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
  ☆10Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated last week
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 6 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year