Alliance VLSI CAD Tools (LIP6)
☆24Aug 28, 2026Updated 2 months ago
Alternatives and similar repositories for alliance
Users that are interested in alliance are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Coriolis VLSI EDA Tool (LIP6)☆94Oct 18, 2026Updated 2 weeks ago
- Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)☆17Oct 18, 2026Updated 2 weeks ago
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- IO and periphery cells for the GF180MCU provided by GlobalFoundries.☆14Dec 3, 2022Updated 3 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 4 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A bit-serial CPU☆20Sep 29, 2019Updated 7 years ago
- RTLMeter benchmark suite☆34Oct 26, 2026Updated last week
- An open-source resistive random access memory (RRAM) compiler based on OpenRAM.☆11Nov 21, 2020Updated 5 years ago
- ☆11Updated this week
- ☆14Jun 21, 2026Updated 4 months ago
- This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efables…☆12Dec 6, 2023Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆19Sep 22, 2026Updated last month
- BuDDy Binary Decision Diagram(BDD) library provisioned with CMake files☆14Apr 1, 2017Updated 9 years ago
- Baseline SoC for Precursor☆16Oct 27, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of a 32-bit single core risc-v platfrom for Xilinx zcu102 board☆13Nov 5, 2019Updated 6 years ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆37Jun 9, 2026Updated 4 months ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- Characterizer☆40Aug 26, 2026Updated 2 months ago
- A Verilog Synthesis Regression Test☆40Jan 19, 2026Updated 9 months ago
- A QSPI Pmod board designed in KiCad containing one Flash and two SPRAMs☆16Feb 21, 2026Updated 8 months ago
- A fork of Yosys that integrates the CellIFT pass☆14Sep 12, 2026Updated last month
- IRSIM switch-level simulator for digital circuits☆39Nov 13, 2025Updated 11 months ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- Library of FPGA architectures☆33Oct 26, 2026Updated last week
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 8 months ago
- A c project for EDIF format parse.☆14May 10, 2016Updated 10 years ago
- Spice to Verilog Converter☆13May 23, 2023Updated 3 years ago
- Low level arithmetic primitives in RTL☆25Apr 3, 2020Updated 6 years ago
- ☆44Jan 26, 2020Updated 6 years ago
- Open source process design kit for 28nm open process☆100Apr 23, 2024Updated 2 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆257Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FOSSi Foundation Website☆19Oct 5, 2024Updated 2 years ago
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆126Updated this week
- ☆22Updated this week
- CRCat: Complex Rational Catalog of all Possible RLC Networks of up to and Including Five Elements☆35Nov 22, 2025Updated 11 months ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆21Updated this week
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆36Oct 15, 2024Updated 2 years ago
- End-to-End Open-Source I2C GPIO Expander☆45Sep 24, 2026Updated last month