Alternatives and similar repositories for meowality

Users that are interested in meowality are comparing it to the libraries listed below

• kbeckmann / pergola_projects
  My pergola FPGA projects
  ☆30Updated 4 years ago
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 4 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• mattvenn / ws2812-core
  verilog core for ws2812 leds
  ☆33Updated 3 years ago
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 6 years ago
• rob-ng15 / PAWS
  PLEASE MOVE TO PAWSv2
  ☆17Updated 3 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆21Updated 4 years ago
• micro-FPGA / CRUVI
  CRUVI Standard Specifications
  ☆19Updated last year
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆42Updated last week
• lambdaconcept / lambdasoc
  ☆44Updated 6 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆42Updated 8 months ago
• pergola-fpga / pergola
  Low-cost ECP5 FPGA development board
  ☆78Updated 5 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated 2 months ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 3 months ago
• GuzTech / ulx3s-nmigen-examples
  nMigen examples for the ULX3S board
  ☆16Updated 4 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆25Updated last week
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆35Updated 4 years ago
• ulx3s / fpga-odysseus
  FPGA Odysseus with ULX3S
  ☆67Updated last year
• whitequark / Yumewatari
  妖刀夢渡
  ☆60Updated 6 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆32Updated 4 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 3 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 8 months ago