☆11Nov 17, 2025Updated 9 months ago
Alternatives and similar repositories for underserved
Users that are interested in underserved are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Development area for another repo: Learn_Bluespec_and_RISCV_Design☆13Jun 28, 2026Updated 2 months ago
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- Home of the open-source EDA course.☆56Jun 12, 2025Updated last year
- Documentation for the 2025 IEEE SSCS Chipathon Track on MOSbius☆19Sep 6, 2025Updated 11 months ago
- An Open-Source Analog Mixed-Signal Chip Design Template & Tutorial for the ihp-sg13g2 Open-PDK☆54Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- a curated "awesome list" of open-source hardware Intellectual Property (IP) blocks designed specifically for the SkyWater 130nm (SKY130) …☆28Apr 18, 2026Updated 4 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- A Fully Open-Source Verilog-to-PCB Flow☆26Jul 7, 2024Updated 2 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆32Jun 5, 2024Updated 2 years ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆34Updated this week
- Calculate Pi using the Leibniz formula.☆11Jan 11, 2017Updated 9 years ago
- Flip flop setup, hold & metastability explorer tool☆52Jul 12, 2026Updated last month
- ☆13Jun 9, 2022Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆15Jan 15, 2024Updated 2 years ago
- ☆157Aug 19, 2026Updated last week
- Hardware-based VMAF☆11Aug 29, 2025Updated last year
- Design of BandGapReference Circuit using Sky130 PDK☆12Oct 30, 2021Updated 4 years ago
- Fault Injection Automatic Test Equipment☆17Nov 22, 2021Updated 4 years ago
- Virtual Development Board☆64Nov 26, 2021Updated 4 years ago
- ☆16Jan 25, 2026Updated 7 months ago
- Analog and RF blocks on Skywaters 130nm☆11Jul 30, 2022Updated 4 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆17Mar 8, 2026Updated 5 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Icestudio examples - Community contributions☆18Jan 27, 2019Updated 7 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆14Aug 26, 2024Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆46Mar 24, 2023Updated 3 years ago
- ☆10Dec 8, 2022Updated 3 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- ☆10Jun 4, 2021Updated 5 years ago
- Design data files for MakeLSI☆11Jul 9, 2016Updated 10 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- KLayout technology files for Skywater SKY130☆44Jul 19, 2023Updated 3 years ago
- Efabless mpw7 submission☆16May 6, 2024Updated 2 years ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆11Jun 7, 2020Updated 6 years ago
- Load bitstream to AG1K series FPGA using CH552☆12Nov 19, 2021Updated 4 years ago
- ☆17Aug 16, 2023Updated 3 years ago
- ECG reconstruction☆16Nov 29, 2023Updated 2 years ago
- Graphical intuition to MOSFET square-law☆12Jan 5, 2021Updated 5 years ago