RTimothyEdwards / capicheLinks
Parasitic capacitance analysis of foundry metal stackups
☆15Updated 5 months ago
Alternatives and similar repositories for capiche
Users that are interested in capiche are comparing it to the libraries listed below
Sorting:
- Characterizer☆30Updated 2 months ago
- PLL Designs on Skywater 130nm MPW☆21Updated last year
- repository for a bandgap voltage reference in SKY130 technology☆40Updated 2 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆25Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆65Updated last month
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆47Updated 7 months ago
- Skywaters 130nm Klayout PDK☆27Updated 8 months ago
- EM simulation scripts to simulate passive devices on Skywater 130nm open-source process. (Octave interface only for now)☆12Updated last year
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆74Updated 6 months ago
- KLayout technology files for Skywater SKY130☆42Updated 2 years ago
- Circuit Automatic Characterization Engine☆50Updated 8 months ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆19Updated 3 months ago
- ☆12Updated 3 years ago
- ☆106Updated 2 weeks ago
- A python3 gm/ID starter kit☆54Updated 2 months ago
- A set of rules and recommendations for analog and digital circuit designers.☆29Updated 11 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆49Updated last month
- Open-source PDK version manager☆27Updated 2 weeks ago
- ☆43Updated 3 years ago
- Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-des…☆66Updated 3 weeks ago
- ☆83Updated 9 months ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated last year
- LAYout with Gridded Objects v2☆65Updated 4 months ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆37Updated 2 months ago
- Reinforcement learning assisted analog layout design flow.☆30Updated last year
- A tiny Python package to parse spice raw data files.☆53Updated 2 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆61Updated this week
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- SG13G2_ASIC-Design-Template☆15Updated 2 months ago