RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
☆34Jan 2, 2024Updated 2 years ago
Alternatives and similar repositories for ethernet-physical-layer
Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below
Sorting:
- ☆21Feb 15, 2023Updated 3 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆60Jan 10, 2024Updated 2 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆81Dec 24, 2023Updated 2 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 5 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- 10G Low Latency Ethernet☆100Jul 15, 2023Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated last week
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated 2 years ago
- ☆10Jan 25, 2023Updated 3 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆31Dec 31, 2022Updated 3 years ago
- DekTec linux driver releases☆12Oct 26, 2023Updated 2 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆20Dec 11, 2023Updated 2 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago
- ☆78Feb 5, 2022Updated 4 years ago
- ☆15Jun 1, 2019Updated 6 years ago
- HW/SW co-designed end-host RPC stack☆20Oct 28, 2021Updated 4 years ago
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆18Aug 25, 2023Updated 2 years ago
- 10Gb Ethernet Switch☆255Oct 16, 2025Updated 4 months ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- FIX-FastTrade is a high-performance electronic trading system that leverages the Financial Information eXchange (FIX) protocol for fast a…☆20Jul 29, 2025Updated 7 months ago
- 2-channel microcontroller servo with EEM and Ethernet based on STM32 CPU☆22Jun 22, 2023Updated 2 years ago
- understanding of cocotb (In Chinese Only)☆21Jun 10, 2025Updated 8 months ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 11 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Nov 25, 2015Updated 10 years ago
- Lithography Hotspot detection using Deep Learning. Source code for the paper.☆21Dec 17, 2018Updated 7 years ago
- Re-coded Xilinx primitives for Verilator use☆52Jun 24, 2025Updated 8 months ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆34Jun 22, 2023Updated 2 years ago
- High-performance eBPF implementation in hardware.☆27Apr 5, 2022Updated 3 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆899Updated this week
- Codes for femtosecond laser interaction research☆13Jun 25, 2025Updated 8 months ago
- Weber State University Senior Project - (Optical Frequency Domain Reflectometry)☆12Feb 28, 2024Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆32May 22, 2023Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 3 years ago
- ☆33Mar 20, 2025Updated 11 months ago
- ☆13Mar 2, 2023Updated 3 years ago