Alternatives and similar repositories for ethernet-physical-layer

Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below

• jjyy-Huang / SpinalHDL-ethernet
  ☆18Updated 2 years ago
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆38Updated last year
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆44Updated 2 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆17Updated 5 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆47Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 6 years ago
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆20Updated 6 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆65Updated last year
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆63Updated 7 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 4 months ago
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆40Updated 3 weeks ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆45Updated 9 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆19Updated 9 months ago
• alexforencich / dma-bench
  ☆27Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago