Essenceia / ethernet-physical-layer
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
☆26Updated last year
Alternatives and similar repositories for ethernet-physical-layer
Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below
Sorting:
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆36Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Ethernet switch implementation written in Verilog☆47Updated last year
- ☆18Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- ☆26Updated 2 years ago
- Implementation of the PCIe physical layer☆39Updated 4 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆25Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Verilog Content Addressable Memory Module☆106Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Open FPGA Modules☆23Updated 7 months ago
- ☆22Updated 8 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- UART models for cocotb☆28Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆37Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- Ethernet interface modules for Cocotb☆63Updated last year