Essenceia / ethernet-physical-layerLinks
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
☆32Updated last year
Alternatives and similar repositories for ethernet-physical-layer
Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below
Sorting:
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆54Updated last year
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- ☆20Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆34Updated last year
- Ethernet 10GE MAC☆46Updated 11 years ago
- ☆76Updated 3 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- ☆80Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- PCI Express controller model☆71Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- Re-coded Xilinx primitives for Verilator use☆50Updated 6 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago
- Ethernet switch implementation written in Verilog☆56Updated 2 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆34Updated 6 years ago
- ☆27Updated 3 years ago
- UART -> AXI Bridge☆68Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago