RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
☆39Jan 2, 2024Updated 2 years ago
Alternatives and similar repositories for ethernet-physical-layer
Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆23Feb 15, 2023Updated 3 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆70Jan 10, 2024Updated 2 years ago
- 10G Low Latency Ethernet☆109Jul 15, 2023Updated 3 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆33Dec 31, 2022Updated 3 years ago
- ☆10Jul 6, 2015Updated 11 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 6 years ago
- ☆82Feb 5, 2022Updated 4 years ago
- FIX-FastTrade is a high-performance electronic trading system that leverages the Financial Information eXchange (FIX) protocol for fast a…☆23Jul 29, 2025Updated last year
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- 10Gb Ethernet Switch☆274Updated this week
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆10Jan 25, 2023Updated 3 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Nov 25, 2015Updated 10 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 12 years ago
- DekTec linux driver releases☆14May 23, 2026Updated 3 months ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆65Aug 21, 2023Updated 3 years ago
- 2-channel microcontroller servo with EEM and Ethernet based on STM32 CPU☆23Jun 22, 2023Updated 3 years ago
- 在线登录注册(android客户端+javaweb服务端+腾讯云服务器+腾讯云数据库)☆10Nov 11, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HW/SW co-designed end-host RPC stack☆20Oct 28, 2021Updated 4 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆24Dec 11, 2023Updated 2 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆957Aug 3, 2026Updated last month
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- Opensource DDR3 Controller☆472Jun 12, 2026Updated 2 months ago
- ☆16Mar 22, 2021Updated 5 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆37Feb 26, 2026Updated 6 months ago
- A data backup software for Linux (UESTC, 软件开发综合实验)☆14Dec 28, 2022Updated 3 years ago
- A tutorial of model quantization using TensorFlow☆11Aug 2, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Re-coded Xilinx primitives for Verilator use☆54Jun 24, 2025Updated last year
- Computer Architecture UIUC SP 2018☆15May 4, 2018Updated 8 years ago
- Notes on Common Lisp Libraries☆17Oct 16, 2024Updated last year
- Verilog RTL Design☆53Sep 4, 2021Updated 4 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Aug 9, 2026Updated 3 weeks ago
- SystemVerilog microarchitecture challenge for AI No.1☆17Aug 6, 2025Updated last year
- Agile Hardware Design Course☆18Updated this week