RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
☆34Jan 2, 2024Updated 2 years ago
Alternatives and similar repositories for ethernet-physical-layer
Users that are interested in ethernet-physical-layer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆61Jan 10, 2024Updated 2 years ago
- ☆23Feb 15, 2023Updated 3 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆87Dec 24, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 10G Low Latency Ethernet☆103Jul 15, 2023Updated 2 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 5 years ago
- ☆15Jun 1, 2019Updated 6 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆21Dec 11, 2023Updated 2 years ago
- ☆79Feb 5, 2022Updated 4 years ago
- FIX-FastTrade is a high-performance electronic trading system that leverages the Financial Information eXchange (FIX) protocol for fast a…☆20Jul 29, 2025Updated 8 months ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆10Jul 6, 2015Updated 10 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- 10Gb Ethernet Switch☆262Oct 16, 2025Updated 5 months ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- ☆10Jan 25, 2023Updated 3 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated 2 years ago
- DekTec linux driver releases☆14Oct 26, 2023Updated 2 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 11 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- 2-channel microcontroller servo with EEM and Ethernet based on STM32 CPU☆23Jun 22, 2023Updated 2 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆913Mar 27, 2026Updated 2 weeks ago
- ☆16Mar 22, 2021Updated 5 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- Verilog RTL Design☆47Sep 4, 2021Updated 4 years ago
- Convert Verilog to a Hardcaml design☆19Apr 6, 2026Updated last week
- Computer Architecture UIUC SP 2018☆14May 4, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated this week
- Re-coded Xilinx primitives for Verilator use☆53Jun 24, 2025Updated 9 months ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆64Aug 21, 2023Updated 2 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆13Oct 24, 2017Updated 8 years ago
- Deep Neural Network inference using Xilinx Zynq-7000 chip.☆29Jun 26, 2020Updated 5 years ago
- A minimalist, low-latency, HFT CME MDP3.0 C++ market data feed handler and pcap file reader (MDP 3.0)☆53Dec 25, 2025Updated 3 months ago
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆18Aug 25, 2023Updated 2 years ago