Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
☆14Feb 16, 2024Updated 2 years ago
Alternatives and similar repositories for FPGA-SystolicArray
Users that are interested in FPGA-SystolicArray are comparing it to the libraries listed below
Sorting:
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆11Dec 26, 2024Updated last year
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆15Dec 14, 2021Updated 4 years ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆31Aug 22, 2024Updated last year
- Resource Utilization and Latency Estimation for ML on FPGA.☆18Feb 4, 2026Updated 3 weeks ago
- A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS☆15Feb 27, 2021Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- Spiking neural network inference engine for 7-Series FPGAs☆26Aug 31, 2025Updated 6 months ago
- CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL☆23Dec 29, 2023Updated 2 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆15Sep 9, 2023Updated 2 years ago
- ☆20Apr 7, 2021Updated 4 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆18Dec 7, 2021Updated 4 years ago
- Offical Implementation of "CLIF: Complementary Leaky Integrate-and-Fire Neuron for Spiking Neural Networks" (ICML 2024 spotlight)☆27Sep 17, 2025Updated 5 months ago
- An automated HDC platform☆11Updated this week
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆26Aug 28, 2016Updated 9 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆37Sep 25, 2019Updated 6 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆38Feb 21, 2018Updated 8 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆33May 20, 2020Updated 5 years ago
- A project demonstrate how to config ad9361 to TX mode