dsa-shua / FPGA-SystolicArrayLinks
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
☆7Updated last year
Alternatives and similar repositories for FPGA-SystolicArray
Users that are interested in FPGA-SystolicArray are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Updated last year
- ☆14Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆16Updated 10 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆49Updated 8 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- ☆25Updated 3 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated last month
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆19Updated 10 months ago
- ☆27Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆29Updated 4 years ago