hguq / HG-PIPE

Related projects ⓘ

Alternatives and complementary repositories for HG-PIPE

• gl9544 / vit_transformer_fpga
  ☆13Updated last year
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆118Updated 7 months ago
• adamgallas / FireFly-v1
  [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…
  ☆15Updated 7 months ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆14Updated last year
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆73Updated 2 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆68Updated 2 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆12Updated 3 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆93Updated 4 years ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆44Updated 3 years ago
• SamsungLabs / Butterfly_Acc
  The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …
  ☆112Updated last year
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆26Updated 2 years ago
• albertomarchisio / SwiftTron
  ☆37Updated last year
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆20Updated last year
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆85Updated 11 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆129Updated 4 years ago
• fffasttime / AnyPackingNet
  ☆24Updated 8 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆33Updated 11 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆32Updated 2 months ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆13Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆32Updated 2 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆40Updated last week
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆12Updated 2 months ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆12Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆48Updated 3 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆16Updated 7 months ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆61Updated last year
• AiArtisan / dac_sdc_2022_champion
  ☆20Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 2 years ago