Alternatives and similar repositories for simd-processor

Users that are interested in simd-processor are comparing it to the libraries listed below

• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆33Updated last year
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆22Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆28Updated 13 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆69Updated 11 months ago
• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆20Updated 2 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆57Updated 5 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆12Updated 4 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆35Updated last month
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆44Updated 11 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 10 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 4 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆28Updated 3 months ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• pulp-platform / jtag_pulp
  ☆13Updated 2 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆35Updated 8 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆20Updated 10 months ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆29Updated last month