Alternatives and similar repositories for simd-processor

Users that are interested in simd-processor are comparing it to the libraries listed below

• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated last year
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆29Updated last year
• efabless / EF_UART
  Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
  ☆13Updated 9 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆69Updated 3 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 9 months ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆42Updated 11 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated 3 weeks ago
• pulp-platform / axi_llc
  ☆30Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated 11 months ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆18Updated 5 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆34Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆54Updated 4 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆11Updated 4 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• pulp-platform / jtag_pulp
  ☆13Updated 2 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆23Updated 2 months ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago