ADS-ENTC / simd-processorLinks
Matrix multiplication accelerator on ZYNQ SoC.
☆11Updated 4 months ago
Alternatives and similar repositories for simd-processor
Users that are interested in simd-processor are comparing it to the libraries listed below
Sorting:
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆29Updated last month
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Updated 9 months ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆16Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 3 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- ☆29Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆35Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- PCI Express controller model☆66Updated 2 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- DMA Hardware Description with Verilog☆17Updated 5 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- ☆20Updated 2 years ago