BrosnanYuen / tt07-Neuromorphic-ASIC-with-96-NeuronsLinks
Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7
☆11Updated last year
Alternatives and similar repositories for tt07-Neuromorphic-ASIC-with-96-Neurons
Users that are interested in tt07-Neuromorphic-ASIC-with-96-Neurons are comparing it to the libraries listed below
Sorting:
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆18Updated 2 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Updated 2 years ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆76Updated 3 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆28Updated last year
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 3 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆63Updated last year
- ☆30Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- RTL Design and Verification☆17Updated 5 years ago
- Fully opensource spiking neural network accelerator☆163Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated this week
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 10 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆26Updated 2 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- This is a tutorial on standard digital design flow☆81Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago