复微杯
☆18Aug 7, 2024Updated 2 years ago
Alternatives and similar repositories for My_Noc
Users that are interested in My_Noc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆35Jul 9, 2025Updated last year
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.☆571Jul 17, 2025Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Deploy llama2.c on the OpenLA500 SoC with custom AI accelerator (FPGA)☆22Jun 16, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- FPGA-based SNN Accelerator Toy☆46Apr 17, 2026Updated 3 months ago
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆22Jul 5, 2026Updated last month
- 包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等☆148Apr 30, 2026Updated 3 months ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 7 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 9 months ago
- Open-source RTL IP developement for IIR/FIR filters in SystemVerilog, along with the C model and verification IP in UVM☆15Jul 8, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆27Jun 30, 2025Updated last year
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 3 months ago
- Network on Chip Implementation written in SytemVerilog☆210Aug 27, 2022Updated 3 years ago
- ESnet general-purpose FPGA design library.☆14Updated this week
- An Open-Source Processor for Accelerating Spiking Neural Network☆14Sep 30, 2022Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 2 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.☆23Aug 1, 2026Updated last week
- ☆24Jul 29, 2026Updated last week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- ☆14Oct 26, 2023Updated 2 years ago
- General Purpose AXI Direct Memory Access☆80May 12, 2024Updated 2 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆14Aug 1, 2023Updated 3 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆28Feb 7, 2023Updated 3 years ago
- 图像去雾与增强☆22Apr 17, 2019Updated 7 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆21May 26, 2021Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- ☆20Jul 30, 2025Updated last year
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆26Feb 16, 2024Updated 2 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆34Aug 22, 2024Updated last year
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆38Updated this week
- Self implementation of course projects for Computer Architecture 2022 Spring☆11Sep 17, 2022Updated 3 years ago