rbarzic / nanorv32Links
A small 32-bit implementation of the RISC-V architecture
☆32Updated 5 years ago
Alternatives and similar repositories for nanorv32
Users that are interested in nanorv32 are comparing it to the libraries listed below
Sorting:
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 6 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- turbo 8051☆29Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- ☆30Updated 8 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 6 months ago
- USB Full Speed PHY☆45Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- A RISC-V processor☆15Updated 6 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Another tiny RISC-V implementation☆56Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆31Updated 7 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- ☆59Updated 3 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated last month
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago