rbarzic / nanorv32Links
A small 32-bit implementation of the RISC-V architecture
☆32Updated 4 years ago
Alternatives and similar repositories for nanorv32
Users that are interested in nanorv32 are comparing it to the libraries listed below
Sorting:
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Platform Level Interrupt Controller☆41Updated last year
- ☆16Updated 6 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- turbo 8051☆29Updated 7 years ago
- ☆59Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A RISC-V processor☆15Updated 6 years ago
- ☆30Updated 2 months ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 5 months ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- ☆26Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Advanced Debug Interface☆15Updated 5 months ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- Generic AXI master stub☆19Updated 10 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago