rbarzic / nanorv32Links
A small 32-bit implementation of the RISC-V architecture
☆32Updated 5 years ago
Alternatives and similar repositories for nanorv32
Users that are interested in nanorv32 are comparing it to the libraries listed below
Sorting:
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 7 months ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 7 months ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- A RISC-V processor☆15Updated 6 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- ☆64Updated 6 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆61Updated 4 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 6 years ago
- JTAG Test Access Port (TAP)☆35Updated 11 years ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago