rbarzic / nanorv32Links
A small 32-bit implementation of the RISC-V architecture
☆32Updated 5 years ago
Alternatives and similar repositories for nanorv32
Users that are interested in nanorv32 are comparing it to the libraries listed below
Sorting:
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- Universal Advanced JTAG Debug Interface☆16Updated last year
- A RISC-V processor☆15Updated 6 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 6 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆47Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Another tiny RISC-V implementation☆59Updated 4 years ago
- RISC-V processor☆32Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated 2 years ago
- ☆60Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago