Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1 in TSMC 16nm
☆23Sep 27, 2026Updated last month
Alternatives and similar repositories for tpu-accelerator-lite
Users that are interested in tpu-accelerator-lite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss dat…☆15Sep 15, 2026Updated last month
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- ☆52Aug 10, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An AI accelerator implementation with Xilinx FPGA☆136Updated this week
- This project is to design yolo AI accelerator in verilog HDL.☆45Oct 8, 2026Updated 3 weeks ago
- ☆12Nov 4, 2025Updated 11 months ago
- ☆20Dec 21, 2020Updated 5 years ago
- Advanced Verification Methodologies for RISC-V and related IP☆10Jan 16, 2023Updated 3 years ago
- ☆13Jan 24, 2026Updated 9 months ago
- GPU-accelerated RePlAce☆14Jun 11, 2024Updated 2 years ago
- ☆24Sep 26, 2025Updated last year
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 2 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Nov 9, 2025Updated 11 months ago
- ☆11Sep 21, 2026Updated last month
- Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host i…☆20May 24, 2026Updated 5 months ago
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆20Mar 30, 2025Updated last year
- A progressive course in digital design and verification covering UART, SPI, and I²C — from specification and RTL through UVM-based verifi…☆20May 30, 2026Updated 4 months ago
- ☆28Jun 21, 2024Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆29Updated this week
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- npu☆13Sep 5, 2018Updated 8 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆18May 17, 2024Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- ☆15Apr 24, 2023Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆14Jun 9, 2026Updated 4 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- A tiniest ASIC GPU that can render only two texture mapped triangles☆31Jan 2, 2026Updated 9 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆48Jan 15, 2024Updated 2 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- Theia: ray graphic processing unit☆22Jul 17, 2014Updated 12 years ago