大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。
☆22Jun 30, 2025Updated 8 months ago
Alternatives and similar repositories for BNN_accelerator
Users that are interested in BNN_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 一个基于 GitHub Actions 的自动化工具，每天早上自动追踪和分析 arXiv 最新论文，并通过邮件发送分析报告。该工具使用 DeepSeek AI 进行论文分析和总结。☆21Jun 20, 2025Updated 9 months ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 3 months ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated last year
- ☆10Dec 15, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Aug 11, 2021Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- ☆21Updated this week
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Learning how to make RISC-V 32bit CPU with Chisel☆70Sep 17, 2021Updated 4 years ago
- study uvm step by step☆11Mar 28, 2019Updated 6 years ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆12Dec 16, 2025Updated 3 months ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆14Nov 12, 2025Updated 4 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆13Aug 1, 2023Updated 2 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Oct 25, 2024Updated last year
- 一个JPEG有损图像压缩编码器☆13May 22, 2023Updated 2 years ago
- Course Project for High Level Chip Design （高层次芯片设计）☆17Jan 2, 2025Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆12Aug 26, 2024Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆19Apr 16, 2025Updated 11 months ago
- ☆11Mar 6, 2020Updated 6 years ago
- 基于玄铁openc906，搭建最小化SoC系统☆19Apr 7, 2025Updated 11 months ago
- This project is to design yolo AI accelerator in verilog HDL.☆34Oct 8, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ECG Classification using PyTorch☆18Jun 27, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- 海思mpp视频处理平台测试代码☆12Sep 22, 2020Updated 5 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- IC设计中的一些经典书籍☆13Jul 28, 2020Updated 5 years ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago
- ☆13Oct 9, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- The screen-oriented text editor for RT-Thread.☆16Apr 20, 2024Updated last year
- 《CPU设计实战》学习记录及代码☆14Dec 30, 2023Updated 2 years ago
- ☆19Sep 12, 2022Updated 3 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆16Jun 11, 2025Updated 9 months ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- ☆12Jun 22, 2023Updated 2 years ago