curryfromuestc / BNN_acceleratorLinks
大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。
☆20Updated 5 months ago
Alternatives and similar repositories for BNN_accelerator
Users that are interested in BNN_accelerator are comparing it to the libraries listed below
Sorting:
- ☆10Updated 3 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- 简单的未优化的SRT除法器☆12Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆143Updated 7 months ago
- ☆45Updated 4 years ago
- CPU Design Based on RISCV ISA☆126Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆122Updated 4 months ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- ☆39Updated 6 years ago
- ☆14Updated 2 years ago
- ☆76Updated 5 years ago
- ☆19Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆26Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- AXI总线连接器☆105Updated 5 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆84Updated 9 months ago
- ☆63Updated 3 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- syn script for DC Compiler☆14Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆63Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆39Updated 3 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- ☆10Updated 5 years ago
- (Not actively updating)Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆21Updated 11 months ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago