VHDLproc is a VHDL preprocessor
☆24May 12, 2022Updated 4 years ago
Alternatives and similar repositories for VHDLproc
Users that are interested in VHDLproc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VHDL related news.☆27Updated this week
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Apr 8, 2026Updated last month
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- ☆27Mar 17, 2026Updated 2 months ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆67Nov 7, 2025Updated 6 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 8 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDL plugin for RgGen☆15Apr 19, 2026Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆51Jun 5, 2022Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆69Feb 16, 2026Updated 3 months ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Apr 10, 2025Updated last year
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 2 years ago
- A JSON library implemented in VHDL.☆84Feb 8, 2026Updated 3 months ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated 3 months ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Updated this week
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated 2 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year
- Building and deploying container images for open source electronic design automation (EDA)☆122Oct 3, 2024Updated last year
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago