Alternatives and similar repositories for fa19-lab-starter:

Users that are interested in fa19-lab-starter are comparing it to the libraries listed below

• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆19Updated 4 years ago
• ucb-eecs251b / sp22-labs
  Contains all labs for EECS 251B for spring 2022
  ☆11Updated 3 years ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 6 months ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆91Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆27Updated 5 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 9 months ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 7 years ago
• sashimi-yzh / educational-materials
  Educational materials for RISC-V
  ☆6Updated 5 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• NJU-ProjectN / nexus-am
  ☆24Updated 5 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• anishagartia / Cache-Coherence
  Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence
  ☆16Updated 8 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆37Updated last year
• 2horse9sun / ucb_sp20_cs152_lab
  UC Berkeley CS152 Computer Architecture and Engineering Labs
  ☆22Updated 4 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 7 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆10Updated 2 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆60Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆44Updated last week
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆10Updated 6 years ago
• LvNA-system / EasyDiff-noop
  ☆10Updated 5 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆33Updated 6 years ago
• miaochenlu / Gem5_tutorials
  ☆19Updated last year
• adithyasunil26 / Y86-64-Processor
  A Y86-64 processor implemented using Verilog
  ☆17Updated 3 years ago