Alternatives and similar repositories for risc-v-simulator

Users that are interested in risc-v-simulator are comparing it to the libraries listed below

• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 4 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 6 months ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• pulp-platform / pulp-freertos
  FreeRTOS for PULP
  ☆13Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆62Updated 9 months ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆52Updated 4 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆101Updated last month
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• RohanNagar / parallel-logic-networks
  Gate-Level Simulation on a GPU
  ☆10Updated 8 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 4 years ago
• lmcad-unicamp / riscv-sbt
  RISC-V Static Binary Translator
  ☆18Updated 6 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆25Updated 2 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• synogate / gatery
  Gatery, a library for circuit design.
  ☆21Updated 9 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated last month
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆19Updated 12 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated 3 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆61Updated last week
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago