Alternatives and similar repositories for risc-v-simulator

Users that are interested in risc-v-simulator are comparing it to the libraries listed below

• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆103Updated 4 years ago
• pulp-platform / pulp-freertos
  FreeRTOS for PULP
  ☆16Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆45Updated 8 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• synogate / gatery
  Gatery, a library for circuit design.
  ☆21Updated 11 months ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆35Updated 5 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆25Updated 8 years ago
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• thinkoco / de10-nano-riscv
  A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
  ☆41Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 3 weeks ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆15Updated last year
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆61Updated 11 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• b224hisl / rioschip
  ☆33Updated 3 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆106Updated 3 months ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆20Updated 11 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• tenstorrent / rv-core-dv-kit
  ☆26Updated 8 months ago