Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
☆26Sep 8, 2024Updated last year
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆27Apr 29, 2024Updated last year
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆52Feb 27, 2026Updated 3 weeks ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- RV64IMAC modelling using System Verilog HDL☆24Aug 10, 2024Updated last year
- ☆15Jul 14, 2024Updated last year
- ☆19Oct 29, 2025Updated 4 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆26Feb 11, 2024Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- A verilog based 5-stage pipelined RISC-V Processor code.☆36Mar 25, 2020Updated 5 years ago
- Compressed Sensing signal decoding with DNN oracle on STM32☆16Apr 5, 2021Updated 4 years ago
- Open source tools for IC design☆13Dec 12, 2024Updated last year
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- I2C master/slave Core☆15Jul 17, 2014Updated 11 years ago
- ARM Guide☆51Jan 4, 2024Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Mar 21, 2020Updated 6 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆63May 8, 2021Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆57Jul 9, 2021Updated 4 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆484Jul 18, 2025Updated 8 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆60Jul 5, 2024Updated last year
- This is a tutorial on standard digital design flow☆83May 24, 2021Updated 4 years ago
- A Keras code on Binary Neural Networks☆21Dec 5, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆77Dec 7, 2020Updated 5 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆21Jul 7, 2024Updated last year
- General Purpose IO with APB4 interface☆15May 10, 2024Updated last year
- ☆33Jul 28, 2020Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- 基于玄铁openc906,搭建最小化SoC系统☆19Apr 7, 2025Updated 11 months ago
- study uvm step by step☆11Mar 28, 2019Updated 6 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago