Juanx65 / RISC-VLinks
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
☆27Updated last year
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- ☆55Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆42Updated 5 months ago
- Static Timing Analysis Full Course☆63Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- A verilog implementation for Network-on-Chip☆81Updated 8 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- ☆40Updated 6 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Simple single-port AXI memory interface☆49Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆22Updated last year
- ☆40Updated 2 weeks ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆39Updated 6 years ago
- ☆70Updated 3 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago