Juanx65 / RISC-VLinks
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
☆22Updated 10 months ago
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below
Sorting:
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆19Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆18Updated last year
- AXI4 BFM in Verilog☆32Updated 8 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆50Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆65Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- Simple single-port AXI memory interface☆42Updated last year
- ☆46Updated 4 years ago
- ☆12Updated 3 months ago
- ☆16Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆19Updated last month
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆33Updated last week
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- ☆56Updated 2 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆87Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- Static Timing Analysis Full Course☆56Updated 2 years ago
- AMBA 3 AHB UVM TB☆32Updated 6 years ago