Juanx65 / RISC-VLinks
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
☆27Updated last year
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆62Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆59Updated last year
- ☆70Updated 3 years ago
- Static Timing Analysis Full Course☆63Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆22Updated 2 years ago
- Simple single-port AXI memory interface☆49Updated last year
- AHB DMA 32 / 64 bits☆59Updated 11 years ago
- ☆55Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆100Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆41Updated 5 years ago
- round robin arbiter☆77Updated 11 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Updated 5 years ago
- Asynchronous fifo in verilog☆38Updated 9 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago