Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
☆28Sep 8, 2024Updated 2 years ago
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- ☆22Oct 29, 2025Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆34Apr 29, 2024Updated 2 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆20Dec 1, 2023Updated 2 years ago
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆59Feb 27, 2026Updated 8 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- RV64IMAC modelling using System Verilog HDL☆28Aug 15, 2026Updated 2 months ago
- ☆17Jul 14, 2024Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 3 years ago
- APB Timer Unit☆14Oct 30, 2025Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- A complete cocotb + VCS + Verdi + Vivado verification environment☆10Nov 25, 2025Updated 11 months ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- This is a tutorial on standard digital design flow☆86May 24, 2021Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆36Mar 21, 2020Updated 6 years ago
- ☆31Feb 22, 2024Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 7 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 7 years ago
- RISC-V compliant Timer IP☆14May 10, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆65Jul 9, 2021Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Advanced Verification Methodologies for RISC-V and related IP☆10Jan 16, 2023Updated 3 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆16Jul 31, 2024Updated 2 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated 2 years ago
- Python wrapper for Xilinx's XSCT/XSDB console☆10Nov 19, 2019Updated 6 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Sep 17, 2023Updated 3 years ago
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- UVM Testbench for synchronus fifo☆21Aug 28, 2020Updated 6 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 3 years ago
- ☆13May 5, 2023Updated 3 years ago
- Compressed Sensing signal decoding with DNN oracle on STM32☆16Apr 5, 2021Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago