Verification IP for Watchdog
☆13Apr 6, 2021Updated 5 years ago
Alternatives and similar repositories for arm_watchdog
Users that are interested in arm_watchdog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- Verification IP for SPI protocol☆21Jul 23, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- To design test bench of the APB protocol☆21Dec 30, 2020Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- UVM Testbench for synchronus fifo☆20Aug 28, 2020Updated 5 years ago
- The memory model was leveraged from micron.☆31Mar 24, 2018Updated 8 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 8 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Verification IP for UART protocol☆25Aug 3, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13May 5, 2023Updated 3 years ago
- ☆30May 11, 2021Updated 5 years ago
- Verification IP for APB protocol☆34Sep 9, 2020Updated 5 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)☆17Nov 10, 2024Updated last year
- A verilog based 5-stage pipelined RISC-V Processor code.☆40Mar 25, 2020Updated 6 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- polar codes encoding and successive cancellation decoding in matlab.☆19Oct 30, 2017Updated 8 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆23Jan 31, 2020Updated 6 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 8 months ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆22Nov 10, 2024Updated last year
- ☆16Mar 27, 2024Updated 2 years ago
- System on Chip verified with UVM/OSVVM/FV☆36Jun 19, 2026Updated last month