kumarraj5364 / AMBA-APB-PROTOCOLLinks
RTL Design and Verification
☆16Updated 4 years ago
Alternatives and similar repositories for AMBA-APB-PROTOCOL
Users that are interested in AMBA-APB-PROTOCOL are comparing it to the libraries listed below
Sorting:
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- To design test bench of the APB protocol☆17Updated 4 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆35Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆47Updated 4 years ago
- Structured UVM Course☆47Updated last year
- ☆20Updated 2 years ago
- ☆12Updated 5 months ago
- System Verilog using Functional Verification☆12Updated last year
- ☆17Updated 2 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- Maven Silicon Project☆19Updated 6 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Design Verification Engineer interview preparation guide.☆34Updated last month
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆62Updated last year
- AXI Interconnect☆52Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆27Updated 13 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Verification IP for APB protocol☆69Updated 4 years ago