Alternatives and similar repositories for 100-Days-Of-RTL:

Users that are interested in 100-Days-Of-RTL are comparing it to the libraries listed below

• Artityagi123456789 / 100DaysofRTL
  ☆16Updated last year
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆23Updated 10 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆23Updated last year
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆13Updated 3 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆32Updated last year
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• Devipriya1921 / VSDBabySoC_ICC2
  ☆10Updated 2 years ago
• Artityagi123456789 / 15DaysofUVM
  ☆14Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆10Updated 8 months ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• ashok-g-r / 100-Days-of-RTL
  ☆15Updated last year
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆109Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆75Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆19Updated last year
• nickson-jose / openlane_build_script
  This script builds openlane and all its dependencies on an Ubuntu (only) System.
  ☆21Updated 2 years ago
• shubhi704 / APB-Protocol
  ☆43Updated 3 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 3 weeks ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆10Updated last year
• ishfaqahmed29 / FIFO_UVM_Verification
  Synchronous FIFO Testbench
  ☆10Updated 3 years ago
• KOTHAVANI / 100-Days-of-RTL-code
  ☆40Updated last year
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆27Updated 6 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆57Updated 2 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆111Updated 2 years ago