Alternatives and similar repositories for DMA-

Users that are interested in DMA- are comparing it to the libraries listed below

• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆26Updated 2 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆53Updated 5 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆39Updated 3 months ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆39Updated 5 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆37Updated 9 years ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆129Updated 9 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆71Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆77Updated 5 years ago
• shubhi704 / APB-Protocol
  ☆52Updated 4 years ago
• MuhammadMajiid / UART
  UART implementation using verilog
  ☆26Updated 2 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆103Updated 2 years ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆17Updated 4 years ago
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆15Updated 10 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆43Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆37Updated 3 years ago
• karimmahmoud22 / SystemVerilog-For-Verification
  ☆39Updated last year
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆32Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆117Updated 2 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated 2 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• karribharathi / 100-Days-of-RTL
  ☆17Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆29Updated 7 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆46Updated 6 years ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆37Updated 6 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆15Updated last year