hell03end / verilog-uartLinks
Simple 8-bit UART realization on Verilog HDL.
☆110Updated last year
Alternatives and similar repositories for verilog-uart
Users that are interested in verilog-uart are comparing it to the libraries listed below
Sorting:
- A simple implementation of a UART modem in Verilog.☆151Updated 3 years ago
- Verilog UART☆178Updated 12 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- Basic RISC-V Test SoC☆140Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆108Updated this week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated this week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- Verilog digital signal processing components☆150Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆76Updated 2 years ago
- Arduino compatible Risc-V Based SOC☆155Updated last year
- RISC-V Nox core☆68Updated last month
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- I2C controller core☆47Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- UART implementation using verilog☆23Updated 2 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- Generic Register Interface (contains various adapters)☆126Updated 2 weeks ago
- Verilog SPI master and slave☆57Updated 9 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆47Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month