Simple 8-bit UART realization on Verilog HDL.
☆118Apr 27, 2024Updated 2 years ago
Alternatives and similar repositories for verilog-uart
Users that are interested in verilog-uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple implementation of a UART modem in Verilog.☆185Nov 10, 2021Updated 4 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆41Oct 3, 2025Updated 8 months ago
- Verilog UART☆198Jun 4, 2013Updated 13 years ago
- UART implementation using verilog☆38Feb 14, 2023Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A simple, basic, formally verified UART controller☆339Jan 29, 2024Updated 2 years ago
- Basic UART TX/RX module for FPGA☆36Oct 18, 2018Updated 7 years ago
- Learn and build GPU RTL from scratch☆21Aug 1, 2025Updated 10 months ago
- Verilog UART☆568Feb 27, 2025Updated last year
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- ☆18Aug 8, 2017Updated 8 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆331Sep 14, 2023Updated 2 years ago
- Implementation of Sobel Filter in Verilog☆28Mar 10, 2017Updated 9 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆454Feb 13, 2026Updated 3 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆82Dec 14, 2023Updated 2 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆600Oct 10, 2021Updated 4 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆45Jul 20, 2023Updated 2 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 7 months ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆11Aug 24, 2024Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆79Dec 7, 2020Updated 5 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 6 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Various HDL (Verilog) IP Cores☆904Jul 1, 2021Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆89Feb 5, 2026Updated 4 months ago
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 8 years ago
- Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)☆23Jan 12, 2020Updated 6 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- ☆17Feb 16, 2023Updated 3 years ago