hell03end / verilog-uart
Simple 8-bit UART realization on Verilog HDL.
☆102Updated last year
Alternatives and similar repositories for verilog-uart:
Users that are interested in verilog-uart are comparing it to the libraries listed below
- A simple implementation of a UART modem in Verilog.☆128Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- Verilog UART☆163Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Verilog digital signal processing components☆133Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆86Updated last year
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Basic RISC-V Test SoC☆122Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- Verilog implementation of a RISC-V core☆115Updated 6 years ago
- This is a detailed SystemVerilog course☆99Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- RISC-V Verification Interface☆89Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- ☆155Updated 2 years ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆81Updated this week
- ☆93Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- Opensource DDR3 Controller☆319Updated 2 weeks ago
- AHB3-Lite Interconnect☆88Updated 11 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago