hell03end / verilog-uartLinks
Simple 8-bit UART realization on Verilog HDL.
☆107Updated last year
Alternatives and similar repositories for verilog-uart
Users that are interested in verilog-uart are comparing it to the libraries listed below
Sorting:
- A simple implementation of a UART modem in Verilog.☆141Updated 3 years ago
- Verilog UART☆173Updated 12 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- Basic RISC-V Test SoC☆137Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- Verilog implementation of a RISC-V core☆121Updated 6 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- RISC-V Nox core☆65Updated 3 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆83Updated 2 years ago
- Arduino compatible Risc-V Based SOC☆153Updated last year
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- A simple DDR3 memory controller☆57Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated this week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆72Updated 2 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Mathematical Functions in Verilog☆93Updated 4 years ago
- Generic Register Interface (contains various adapters)☆123Updated last month
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆57Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆50Updated last year
- RISC-V Verification Interface☆97Updated last month
- ☆95Updated last year