RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
☆21Jun 3, 2023Updated 2 years ago
Alternatives and similar repositories for RISCV_Verilog
Users that are interested in RISCV_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Mini RISC-V SOC☆12Nov 13, 2015Updated 10 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆21Jul 18, 2019Updated 6 years ago
- RISCV SoftCPU Contest 2018☆14Nov 17, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require …☆36Aug 12, 2020Updated 5 years ago
- Research about dataflow architecture☆14Nov 30, 2023Updated 2 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- Verilog implementation of a RISC-V core☆139Oct 11, 2018Updated 7 years ago
- ☆16Jul 30, 2021Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- CGRA framework with vectorization support.☆48May 15, 2026Updated 2 weeks ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Hardware Design of Ascon☆42Apr 13, 2026Updated last month
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 4 years ago
- 🎞️ NoC router in Verilog with FIFO☆15Sep 1, 2022Updated 3 years ago
- PyTorch code for full quantization of DNN using BCGD☆14Jul 24, 2019Updated 6 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- Fully Homomorphic Encryption Compiler☆18Jan 27, 2025Updated last year
- Verdvana‘s Blog☆22Updated this week
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- ☆26Nov 7, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- 这是武汉大学WHU 计算机组成与设计 RISC-V CPU 流水线设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。☆33May 21, 2024Updated 2 years ago
- 一个五子棋人机对战AI,界面用pygame,方法用minmax搜索☆11May 14, 2017Updated 9 years ago
- RISC V core implementation using Verilog.☆30Mar 27, 2021Updated 5 years ago
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆19Mar 6, 2025Updated last year
- 基于极小极大算法的中国象棋对弈程序☆11May 11, 2021Updated 5 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- ☆23Jun 23, 2024Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- mumax3 with sot(spin orbit torque)☆11Mar 3, 2023Updated 3 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- ☆19Jul 21, 2020Updated 5 years ago
- Programmable System on Chip for control of atomic physics experiments☆11Sep 13, 2022Updated 3 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago