RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
☆21Jun 3, 2023Updated 2 years ago
Alternatives and similar repositories for RISCV_Verilog
Users that are interested in RISCV_Verilog are comparing it to the libraries listed below
Sorting:
- Mini RISC-V SOC☆12Nov 13, 2015Updated 10 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- ☆12Nov 26, 2024Updated last year
- Pipelined RISC-V CPU☆26Jun 9, 2021Updated 4 years ago
- Automatically collect and summarize articles from WeChat Official Accounts, using LLM and Feishu doc.☆13Oct 15, 2024Updated last year
- A template to create your own literature survey engine☆11Mar 2, 2026Updated last week
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆35Aug 12, 2020Updated 5 years ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Apr 13, 2023Updated 2 years ago
- An unofficial Typst template for Shanghai Jiao Tong University course general laboratory reports.☆13Mar 1, 2026Updated last week
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Dec 7, 2025Updated 3 months ago
- This repository contains getting started projects related to all PSoC4 pioneer kits.☆13Oct 30, 2018Updated 7 years ago
- CGRA framework with vectorization support.☆44Updated this week
- mumax3 with sot(spin orbit torque)☆11Mar 3, 2023Updated 3 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆11May 2, 2022Updated 3 years ago
- PyTorch code for full quantization of DNN using BCGD☆14Jul 24, 2019Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- Yet another parser for the ABC Notation☆11Dec 8, 2025Updated 3 months ago
- Adds support for the NBT format used by Minecraft to Intellij☆10Jan 1, 2026Updated 2 months ago
- QQ 群验证机器人☆10Nov 9, 2021Updated 4 years ago
- Processor CI project Website☆10Jul 1, 2025Updated 8 months ago
- A VSCode dark theme with vivid colors☆11Apr 29, 2024Updated last year
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- Quantized training method for RRAM-based systems.☆12Sep 24, 2018Updated 7 years ago
- This repository contains a comprehensive collection of parameterized and configurable RTL modules written in Verilog, organized by catego…☆17Sep 23, 2025Updated 5 months ago
- wechat robot framework.☆13Jun 7, 2024Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Experimental process viewer which also supports AIX, Linux and Mac☆13Aug 19, 2025Updated 6 months ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Dec 3, 2023Updated 2 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Nov 28, 2019Updated 6 years ago
- Render custom images on maps (BDSx)☆11Jul 5, 2021Updated 4 years ago
- ☆19Jun 23, 2024Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- ☆14May 15, 2023Updated 2 years ago
- a KaTeX plugin for Markdown-it☆12Jun 3, 2024Updated last year