5 Day TCL begginer to advanced training workshop by VSD
☆20Oct 18, 2023Updated 2 years ago
Alternatives and similar repositories for yosys-tcl-ui-report
Users that are interested in yosys-tcl-ui-report are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆17Feb 16, 2023Updated 3 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆131May 14, 2022Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆40Jul 23, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Sep 27, 2022Updated 3 years ago
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated last year
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆101Apr 25, 2026Updated 4 months ago
- ☆19Feb 26, 2024Updated 2 years ago
- ☆25Nov 11, 2025Updated 9 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 2 years ago
- ☆25Feb 10, 2024Updated 2 years ago
- Implementation of RISC-V RV32I☆35Aug 30, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆72Apr 13, 2024Updated 2 years ago
- This repository is a detailed summary of RTL design using sky130 PDK organized by VLSI System Design☆28Jun 1, 2025Updated last year
- RISC-V Online Help☆36May 27, 2026Updated 3 months ago
- opensource EDA tool flor VLSI design☆38Sep 17, 2023Updated 2 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog☆10Sep 26, 2022Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 4 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- Collection of simple interfaces for Digilent Pmods☆13Aug 3, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆44Mar 28, 2022Updated 4 years ago
- A boilerplate for a freeCodeCamp project.☆20Aug 12, 2026Updated 3 weeks ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 11 months ago
- ⭐ A curated list of my GitHub starred repos, daily updates☆16Sep 28, 2024Updated last year
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆15Aug 2, 2026Updated last month
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- ☆23May 21, 2023Updated 3 years ago
- Verilog RTL Design☆53Sep 4, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.