Alternatives and similar repositories for yosys-tcl-ui-report

Users that are interested in yosys-tcl-ui-report are comparing it to the libraries listed below

• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆24Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆25Updated last month
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated 2 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆12Updated last year
• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆38Updated 2 months ago
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• kerimturak / tcore-rv32imc
  ☆13Updated 6 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆96Updated 2 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆26Updated last year
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆14Updated 3 years ago
• harshithsn / Universal-Shift-Register
  This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…
  ☆11Updated 3 years ago
• shubhi704 / APB-Protocol
  ☆48Updated 4 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆116Updated last year
• Devipriya1921 / VSDBabySoC_ICC2
  ☆13Updated 3 years ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆43Updated 3 years ago
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• VardhanSuroshi / VLSI-ASIC-Design-Flow
  This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…
  ☆21Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆66Updated 3 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆85Updated last year
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆60Updated 2 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated 2 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆34Updated 2 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆37Updated 2 months ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆156Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆42Updated 2 years ago