techvinodreddy / UART-IP-CORE16550A-Verification-UVMLinks
The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry-standard National Semiconductors’ 16550A devic…
☆18Updated 4 years ago
Alternatives and similar repositories for UART-IP-CORE16550A-Verification-UVM
Users that are interested in UART-IP-CORE16550A-Verification-UVM are comparing it to the libraries listed below
Sorting:
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆27Updated 3 years ago
- Verification IP for APB protocol☆73Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆103Updated 2 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Updated 5 years ago
- UART design in SV and verification using UVM and SV☆51Updated 6 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆54Updated 5 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆24Updated last year
- This course walks you through the Linux OS commands and usage.☆19Updated 3 years ago
- ☆52Updated 4 years ago
- SystemVerilog VIP for AMBA APB protocol☆82Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆43Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆39Updated 3 months ago
- Maven Silicon Project☆19Updated 7 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- Verification IP for I2C protocol☆50Updated 4 years ago
- UVM AHB VIP☆90Updated 3 months ago
- ☆46Updated 2 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Updated 8 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆114Updated last year
- VIP for AXI Protocol☆161Updated 3 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆33Updated 5 years ago
- Verification IP for APB protocol☆30Updated 5 years ago
- UVM examples and projects☆152Updated 6 months ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆58Updated 5 years ago
- System Verilog using Functional Verification☆12Updated last year
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆157Updated 5 years ago
- SystemVerilog UVM testbench example☆37Updated last year
- a very simple risc_cpu verification demo with uvm☆26Updated 6 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆31Updated 10 months ago