Alternatives and similar repositories for UART-IP-CORE16550A-Verification-UVM:

Users that are interested in UART-IP-CORE16550A-Verification-UVM are comparing it to the libraries listed below

• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 4 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆39Updated 5 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆22Updated 2 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆38Updated 4 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆17Updated 6 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆40Updated 3 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆22Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆16Updated 2 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆28Updated 2 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆18Updated 5 months ago
• VimfulDang / APB-SPI-Controller-Verification
  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…
  ☆8Updated 3 weeks ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆25Updated 4 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆29Updated 4 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆17Updated 3 years ago
• ishfaqahmed29 / FIFO_UVM_Verification
  Synchronous FIFO Testbench
  ☆10Updated 2 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆17Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 6 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆80Updated last year
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆56Updated last year
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆19Updated 5 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆36Updated 4 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆36Updated last year
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆14Updated 3 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆29Updated 3 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆29Updated 8 months ago
• shubhi704 / APB-Protocol
  ☆38Updated 3 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆18Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆14Updated 6 years ago