This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
☆15Mar 30, 2022Updated 4 years ago
Alternatives and similar repositories for ASIC-Implementation-UART
Users that are interested in ASIC-Implementation-UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- APB Timer Unit☆14Oct 30, 2025Updated 9 months ago
- ☆17Feb 16, 2023Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆23Apr 15, 2021Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- EE 287 2012 Fall☆34Mar 11, 2013Updated 13 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- ARM-CPU implemented verilog☆30Jan 13, 2024Updated 2 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆19Jan 28, 2022Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆30Apr 29, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- To design test bench of the APB protocol☆21Dec 30, 2020Updated 5 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆27Aug 11, 2022Updated 3 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆30Jul 1, 2026Updated last month
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆12Dec 27, 2021Updated 4 years ago
- Pipelined RISC-V CPU☆28Jun 9, 2021Updated 5 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆127Feb 22, 2024Updated 2 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SpringBoot 各模块整合 - 入门项目,包含:atomikos, shiro, mybatis, mybatis-plus, jpa, jdbc-template, redis, mongodb, docker, jpa, admin, asynchronous, …☆12Jul 20, 2023Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆51Dec 3, 2023Updated 2 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 6 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- I was missing turboc, so I wanted to recreate and modernise the color scheme☆18Oct 8, 2024Updated last year
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated 2 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆37Dec 24, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- The template for VLSI project☆27May 10, 2019Updated 7 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago