This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
☆15Mar 30, 2022Updated 3 years ago
Alternatives and similar repositories for ASIC-Implementation-UART
Users that are interested in ASIC-Implementation-UART are comparing it to the libraries listed below
Sorting:
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 9 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Apr 15, 2021Updated 4 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- EE 287 2012 Fall☆32Mar 11, 2013Updated 13 years ago
- Single Port RAM, Dual Port RAM, FIFO☆33May 17, 2022Updated 3 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- ARM-CPU implemented verilog☆29Jan 13, 2024Updated 2 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆17Jan 28, 2022Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆27Apr 29, 2024Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆26Aug 11, 2022Updated 3 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Dec 3, 2023Updated 2 years ago
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- I was missing turboc, so I wanted to recreate and modernise the color scheme☆17Oct 8, 2024Updated last year
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated last year
- SpringBoot 各模块整合 - 入门项目,包含:atomikos, shiro, mybatis, mybatis-plus, jpa, jdbc-template, redis, mongodb, docker, jpa, admin, asynchronous, …☆12Jul 20, 2023Updated 2 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- Simple 8-bit UART realization on Verilog HDL.☆115Apr 27, 2024Updated last year
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Dec 24, 2020Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆108Feb 22, 2024Updated 2 years ago
- General Purpose IO with APB4 interface☆15May 10, 2024Updated last year
- A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.☆17Mar 25, 2023Updated 2 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- Turtle grammar for tree-sitter☆11Jul 2, 2024Updated last year
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago