abdelazeem201 / ASIC-Implementation-UARTLinks
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
☆15Updated 3 years ago
Alternatives and similar repositories for ASIC-Implementation-UART
Users that are interested in ASIC-Implementation-UART are comparing it to the libraries listed below
Sorting:
- To design test bench of the APB protocol☆18Updated 4 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆14Updated 2 years ago
- RTL Design and Verification☆17Updated 4 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated 2 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- UART models for cocotb☆32Updated 3 months ago
- UART -> AXI Bridge☆67Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Structured UVM Course☆53Updated last year
- Asynchronous fifo in verilog☆37Updated 9 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- ☆37Updated 6 months ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆39Updated 5 months ago
- ☆17Updated 2 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 10 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆15Updated 5 years ago
- System Verilog using Functional Verification☆12Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- ☆19Updated 3 years ago
- Verilog RTL Design☆46Updated 4 years ago
- A Verilog implementation of a processor cache.☆34Updated 7 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago