Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Branch Prediction, and the Five pipeline stages are simulated and verified the functional testing with test benches on ModelSim.
☆37Aug 12, 2020Updated 5 years ago
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 4 years ago
- My solution to the problem set on HDLBits.☆28Aug 6, 2020Updated 5 years ago
- A sudoku puzzle game made by Bevy game engine☆13May 9, 2025Updated last year
- ☆14Sep 27, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This repository contains the design files of RISC-V Single Cycle Core☆85Dec 14, 2023Updated 2 years ago
- Cost effective DIY DCC Decoder for model railroad locomotives☆10Sep 16, 2024Updated last year
- 中科大 2017 级数字电路实验/组成原理实验的同学经验和资料分享☆12Oct 25, 2019Updated 6 years ago
- ☆14May 22, 2026Updated last month
- ☆14Aug 3, 2021Updated 4 years ago
- PS2 interface☆18Dec 4, 2017Updated 8 years ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- OpenMPL (Open Math Performance Library) is an open source math libraries, including BLAS, LAPACK, FFT, VML, and others.☆23Aug 15, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 内核crash分析☆23Oct 5, 2023Updated 2 years ago
- A PCB for the Ben Eater 6502 series "Hello, World! from scratch"☆14Jan 13, 2021Updated 5 years ago
- Fast, compact floating point math for ARM Cortex-M0+ MCUs.☆12Jun 16, 2026Updated 2 weeks ago
- This repository contains getting started projects related to all PSoC4 pioneer kits.☆14Oct 30, 2018Updated 7 years ago
- RISC V core implementation using Verilog.☆30Mar 27, 2021Updated 5 years ago
- A library that emulates the 6502☆21Aug 17, 2024Updated last year
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- FPGA raycaster engine written in verilog☆13Apr 19, 2019Updated 7 years ago
- ☆24Jun 23, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Official repository for Color Equivariant Convolutional Networks.☆10Nov 16, 2023Updated 2 years ago
- Pipelined RISC-V CPU☆28Jun 9, 2021Updated 5 years ago
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated 4 months ago
- Programmable System on Chip for control of atomic physics experiments☆11Sep 13, 2022Updated 3 years ago
- GB 开发资源列表☆15Dec 14, 2022Updated 3 years ago
- Rust compile-time type information experiment☆19Jan 24, 2023Updated 3 years ago
- Nanoscale logging library in C++11☆14Dec 15, 2021Updated 4 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- The Original Nintendo Gameboy in Verilog☆61Dec 12, 2014Updated 11 years ago
- simulator for riscv instruction set☆25Sep 24, 2022Updated 3 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 5 years ago
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Trying to get a new skill☆38Dec 31, 2024Updated last year