Alternatives and similar repositories for RISC-V

Users that are interested in RISC-V are comparing it to the libraries listed below

• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆320Updated 7 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆138Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆160Updated 6 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆117Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆172Updated 3 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆112Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 5 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆215Updated last week
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆53Updated 5 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆54Updated last month
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆61Updated last month
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 3 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆82Updated 6 years ago
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆159Updated 2 months ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆144Updated last year
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆149Updated 9 years ago
• saursin / riscv-atom
  An open-source 32-bit RISC-V soft-core processor
  ☆40Updated 2 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆143Updated 5 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆197Updated last year
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆71Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated last week
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆60Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆129Updated 7 years ago