Alternatives and similar repositories for RISC-V

Users that are interested in RISC-V are comparing it to the libraries listed below

• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆306Updated 7 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆144Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆135Updated 5 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆145Updated 5 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆208Updated 3 months ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆112Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆110Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆164Updated 3 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆52Updated 5 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆140Updated last year
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆126Updated 10 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆115Updated last month
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆195Updated 3 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆156Updated last year
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆56Updated last year
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆65Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 6 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆41Updated 4 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆65Updated 3 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆85Updated 3 years ago
• stnolting / riscv-gcc-prebuilt
  📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
  ☆104Updated 7 months ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆322Updated 9 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆60Updated last week
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆155Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• jamieiles / uart
  Verilog UART
  ☆181Updated 12 years ago