tdene / synth_opt_adders
Prefix tree adder space exploration library
☆55Updated this week
Related projects ⓘ
Alternatives and complementary repositories for synth_opt_adders
- An automatic clock gating utility☆43Updated 4 months ago
- ☆29Updated 2 months ago
- ☆36Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆36Updated last month
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- ☆76Updated 8 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- slang-based frontend for Yosys☆43Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆56Updated this week
- ☆76Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- A command-line tool for displaying vcd waveforms.☆47Updated 9 months ago
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Mutation Cover with Yosys (MCY)☆77Updated 2 weeks ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆62Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆58Updated 3 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- ☆45Updated 2 months ago
- ☆30Updated last year
- ☆39Updated last year
- Characterizer☆21Updated 2 months ago
- ☆52Updated last year
- ☆20Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆26Updated last month
- PLL Designs on Skywater 130nm MPW☆20Updated 11 months ago