tdene / synth_opt_addersLinks
Prefix tree adder space exploration library
☆56Updated last year
Alternatives and similar repositories for synth_opt_adders
Users that are interested in synth_opt_adders are comparing it to the libraries listed below
Sorting:
- An automatic clock gating utility☆51Updated 9 months ago
- ☆38Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- ☆38Updated 3 years ago
- ☆88Updated 3 months ago
- ☆33Updated last year
- Characterizer☆31Updated 2 months ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆90Updated last week
- SystemVerilog frontend for Yosys☆187Updated last week
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆50Updated 10 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated last month
- Example of how to use UVM with Verilator☆32Updated last month
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- Fabric generator and CAD tools graphical frontend☆17Updated 5 months ago
- Coriolis VLSI EDA Tool (LIP6)☆76Updated 2 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆77Updated last month
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆35Updated 6 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 11 months ago