tdene / synth_opt_addersLinks
Prefix tree adder space exploration library
☆56Updated last week
Alternatives and similar repositories for synth_opt_adders
Users that are interested in synth_opt_adders are comparing it to the libraries listed below
Sorting:
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- An automatic clock gating utility☆52Updated 9 months ago
- ☆38Updated 3 years ago
- ☆91Updated 3 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆38Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆90Updated 3 weeks ago
- ☆33Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆51Updated 10 months ago
- WAL enables programmable waveform analysis.☆164Updated 3 months ago
- Characterizer☆31Updated 2 months ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆24Updated 3 years ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Updated last year
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆119Updated 4 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆80Updated last week
- Specification of the Wishbone SoC Interconnect Architecture☆51Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Coriolis VLSI EDA Tool (LIP6)☆77Updated 2 weeks ago
- an inverter drawn in magic with makefile to simulate☆27Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Example of how to use UVM with Verilator☆34Updated 2 months ago
- SpiceBind – spice inside HDL simulator☆56Updated 7 months ago