Alternatives and similar repositories for vlsiffra

Users that are interested in vlsiffra are comparing it to the libraries listed below

• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆118Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆120Updated 4 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆144Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated 2 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆184Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• pieter3d / simview
  ☆88Updated 2 months ago
• efabless / chipignite-resources
  ☆85Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated last month
• pulp-platform / svase
  ☆33Updated 11 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated this week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated 2 months ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last week