Alternatives and similar repositories for vlsiffra

Users that are interested in vlsiffra are comparing it to the libraries listed below

• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆107Updated 4 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆141Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆151Updated last week
• bsc-loca / sargantana
  ☆107Updated last week
• pieter3d / simview
  ☆79Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆208Updated 5 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• efabless / chipignite-resources
  ☆83Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• pulp-platform / cheshire-ihp130-o
  ☆49Updated 4 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆193Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆89Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated last month
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆80Updated this week
• pulp-platform / svase
  ☆32Updated 7 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated this week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 2 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆132Updated this week