Create fast and efficient standard cell based adders, multipliers and multiply-adders.
☆120Sep 20, 2023Updated 2 years ago
Alternatives and similar repositories for vlsiffra
Users that are interested in vlsiffra are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Nov 10, 2025Updated 3 months ago
- ☆16Jan 25, 2026Updated last month
- Prefix tree adder space exploration library☆56Jan 27, 2026Updated last month
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 8 months ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- SAR ADC on tiny tapeout☆47Jan 29, 2025Updated last year
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Modular hardware build system☆1,131Updated this week
- design and verification of asynchronous circuits☆43Feb 27, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 3 weeks ago
- An open-source static random access memory (SRAM) compiler.☆1,016Jan 16, 2026Updated last month
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆334Dec 2, 2025Updated 3 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆18Jun 16, 2022Updated 3 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆682Feb 25, 2026Updated last week
- Open source process design kit for 28nm open process☆72Apr 23, 2024Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆25Feb 5, 2023Updated 3 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Jul 21, 2022Updated 3 years ago
- A configurable SRAM generator☆58Updated this week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆218Feb 23, 2026Updated last week
- Parasitic capacitance analysis of foundry metal stackups☆17Jan 12, 2026Updated last month
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- ☆17Aug 16, 2023Updated 2 years ago
- An automatic clock gating utility☆52Apr 15, 2025Updated 10 months ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆34Feb 14, 2024Updated 2 years ago
- ☆14May 24, 2025Updated 9 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆318Oct 22, 2025Updated 4 months ago
- This repository is for (pre-)release versions of the Revolution EDA.☆60Feb 24, 2026Updated last week
- AMC: Asynchronous Memory Compiler☆53Jun 29, 2020Updated 5 years ago
- sram/rram/mram.. compiler☆47Sep 11, 2023Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆123Jul 22, 2021Updated 4 years ago
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆469May 31, 2023Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 3 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- ☆339Jan 13, 2026Updated last month