☆32Sep 3, 2025Updated last year
Alternatives and similar repositories for librelane_summary
Users that are interested in librelane_summary are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆176Nov 10, 2025Updated 11 months ago
- HeiChips 2026 LibreLane Workshop☆16Aug 7, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆22Jun 25, 2026Updated 4 months ago
- ☆16May 23, 2024Updated 2 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- Pci Express eXternalizer lets you pull a PCIE1x port outside of your case using a usb3 cable☆11Aug 2, 2015Updated 11 years ago
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆25Oct 17, 2026Updated 2 weeks ago
- ☆39Jul 11, 2022Updated 4 years ago
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆75Sep 12, 2026Updated last month
- Open source designs developed with the IHP 130nm BiCMOS Open PDK in the FMD_QNC project. Documentation at https://ihp-open-designlib.read…☆78Oct 15, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Analog and power building blocks for sky130 pdk☆23Mar 3, 2021Updated 5 years ago
- Sphinx extension for embedding KiCAD board views created with PcbDraw☆12Jun 27, 2021Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆41Jun 2, 2021Updated 5 years ago
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 6 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- ☆13Jan 25, 2023Updated 3 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,992Mar 25, 2026Updated 7 months ago
- Mirror of tachyon-da cvc Verilog simulator☆58Mar 16, 2026Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fabric generator and CAD tools graphical frontend☆19Oct 6, 2026Updated 3 weeks ago
- Characterizer☆40Aug 26, 2026Updated 2 months ago
- ☆16May 11, 2022Updated 4 years ago
- Cache-accel: FPGA Accelerated Multi-Core Cache Simulator☆14Mar 12, 2022Updated 4 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- ☆42Feb 28, 2022Updated 4 years ago
- RISC-V 32-bit CPU written in amaranth (python-lib)☆14Sep 23, 2024Updated 2 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Tiny Tapeout project build tools + chip integration scripts☆37Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆99Sep 17, 2022Updated 4 years ago
- ☆422Apr 13, 2023Updated 3 years ago
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆20Oct 24, 2026Updated last week
- KianV GF180 ASIC runs ulinux, linux and XV6☆17Jan 15, 2026Updated 9 months ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- The SoC for the introduction to chip design course spring 2026☆21May 22, 2026Updated 5 months ago