Alternatives and similar repositories for RISC-V_CPU

Users that are interested in RISC-V_CPU are comparing it to the libraries listed below

• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆120Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 7 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 4 months ago
• dhschall / LLBP
  Branch predictor simulation framework for the Last-Level Branch Predictor
  ☆27Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆59Updated 6 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆71Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆98Updated last year
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆41Updated 9 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• ecolab-nus / lisa
  A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.
  ☆39Updated 2 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆281Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆74Updated last month
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆77Updated 5 years ago
• CMU-SAFARI / Pythia
  A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (ht…
  ☆150Updated 6 months ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆250Updated 3 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago
• harvard-acc / smaug
  SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
  ☆113Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆212Updated 2 months ago
• OpenXiangShan / GEM5
  ☆104Updated this week
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆75Updated last month
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆224Updated 2 years ago
• hpsresearchgroup / scarab
  Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator
  ☆80Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆138Updated 4 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 11 months ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆17Updated 10 months ago
• dhschall / gem5-fdp
  Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
  ☆26Updated this week
• sangjae4309 / gem5-ramulator2
  This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…
  ☆12Updated 4 months ago