RipperJ / FADOLinks
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
☆25Updated 2 years ago
Alternatives and similar repositories for FADO
Users that are interested in FADO are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆91Updated 10 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆18Updated 3 years ago
- ☆62Updated 9 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆57Updated 5 months ago
- ☆56Updated 6 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆19Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 8 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- CGRA Compilation Framework☆91Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆43Updated last year
- An Open-Source Tool for CGRA Accelerators☆28Updated 4 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆23Updated last year
- A list of our chiplet simulaters☆47Updated 6 months ago
- ☆60Updated 2 years ago
- ☆18Updated 8 months ago
- ☆32Updated last year
- EQueue Dialect☆41Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- ☆10Updated 2 years ago
- agile hardware-software co-design☆52Updated 4 years ago
- ☆13Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 5 months ago