RipperJ / FADO
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
☆23Updated last year
Related projects ⓘ
Alternatives and complementary repositories for FADO
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆21Updated last month
- ☆15Updated 2 years ago
- A graph linear algebra overlay☆49Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- ☆33Updated 3 years ago
- CGRA framework with vectorization support.☆19Updated this week
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆37Updated last year
- ☆10Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆36Updated 6 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆22Updated 2 months ago
- ☆25Updated 3 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆19Updated this week
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆34Updated 4 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- ☆24Updated 7 months ago
- EQueue Dialect☆39Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆26Updated 4 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆13Updated last month
- Dataset for ML-guided Accelerator Design☆31Updated this week
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆13Updated 5 months ago
- ☆31Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆52Updated 2 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆21Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆46Updated 2 weeks ago