[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
☆25Feb 14, 2023Updated 3 years ago
Alternatives and similar repositories for FADO
Users that are interested in FADO are comparing it to the libraries listed below
Sorting:
- SCARIF is a tool to estimate the embodied carbon emissions of data center servers with accelerator hardware (GPUs, FPGAs, etc.)☆15Updated this week
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- ☆17Aug 29, 2024Updated last year
- [DAC2024] Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration☆10Oct 31, 2024Updated last year
- RISC-V 32i Pipeline CPU and Assembler☆18May 6, 2022Updated 3 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 4 years ago
- MLIR+EqSat☆26Jan 10, 2026Updated 2 months ago
- ☆43Mar 31, 2025Updated 11 months ago
- ☆29Jun 10, 2019Updated 6 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 4 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆185Mar 8, 2026Updated 2 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆168Mar 12, 2026Updated last week
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆26May 18, 2025Updated 10 months ago
- ☆12Aug 5, 2023Updated 2 years ago
- ☆16Oct 25, 2022Updated 3 years ago
- ☆13Jun 20, 2023Updated 2 years ago
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆54Jun 6, 2024Updated last year
- Data-Centric MLIR dialect☆46Oct 16, 2023Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Oct 3, 2023Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Feb 6, 2020Updated 6 years ago
- ☆61Aug 4, 2023Updated 2 years ago
- The template for VLSI project☆27Mar 3, 2023Updated 3 years ago
- Multimodal Relational Graph Convolution Network☆21Aug 4, 2023Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Dec 19, 2025Updated 3 months ago
- C++17 implementation of an AST for Verilog code generation☆24Jun 14, 2023Updated 2 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆11May 3, 2019Updated 6 years ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 8 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆36Mar 12, 2026Updated last week
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Updated this week
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆110Mar 9, 2024Updated 2 years ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆69May 9, 2023Updated 2 years ago
- ILAng documentation☆10Nov 2, 2025Updated 4 months ago
- npcomp - An aspirational MLIR based numpy compiler☆51Jul 31, 2020Updated 5 years ago
- work in progress, playing around with btor2 in rust☆12Feb 24, 2026Updated 3 weeks ago
- ☆25May 9, 2019Updated 6 years ago