Alternatives and similar repositories for FADO

Users that are interested in FADO are comparing it to the libraries listed below

• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 5 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆57Updated 5 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆68Updated 4 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆60Updated 10 months ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated 2 years ago
• hngenc / stellar
  ☆31Updated 9 months ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆46Updated last month
• pnnl / soda-opt
  ☆49Updated 2 months ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated last month
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆86Updated 2 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆129Updated 5 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 7 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆36Updated 2 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆73Updated 2 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 9 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆26Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• cornell-zhang / quickest
  QuickEst repository: Quick Estimation of Quality of Results
  ☆26Updated 6 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆51Updated 3 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆24Updated 3 months ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆52Updated last year
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆174Updated 2 weeks ago