Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
☆123May 14, 2025Updated last year
Alternatives and similar repositories for verismith
Users that are interested in verismith are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Good Data Movement manifesto.☆15Nov 18, 2019Updated 6 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆100Jan 29, 2026Updated 8 months ago
- DASS HLS Compiler☆30Oct 4, 2023Updated 3 years ago
- ☆10Oct 26, 2016Updated 9 years ago
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- FPGA synthesis tool powered by program synthesis☆56Dec 15, 2025Updated 9 months ago
- PicoRV☆45Feb 19, 2020Updated 6 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆63Mar 17, 2022Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- A Verilog Synthesis Regression Test☆40Jan 19, 2026Updated 8 months ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Oct 4, 2026Updated last week
- SystemVerilog to Verilog conversion☆754Aug 18, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog design elaborator into word-level netlist form☆251Updated this week
- Build Customized FPGA Implementations for Vivado☆391Updated this week
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 5 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- FPGA synthesis tool powered by equality saturation and program synthesis.☆15Jan 9, 2026Updated 9 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 9 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,238Updated this week
- RTLCheck☆26Oct 9, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆43Apr 13, 2025Updated last year
- SystemVerilog compiler and language services☆1,158Updated this week
- Experiments with Yosys cxxrtl backend☆49Jan 16, 2025Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- Optimization results for superconducting electronic (SCE) circuits☆19Dec 5, 2023Updated 2 years ago
- ☆11May 12, 2025Updated last year
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- An Open-source FPGA IP Generator☆1,160Updated this week
- IceCore Ice40 HX based modular core☆46Jan 23, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆106Jun 27, 2022Updated 4 years ago
- Fast Symbolic Repair of Hardware Design Code☆40Jan 20, 2025Updated last year
- work in progress, playing around with btor2 in rust☆16Oct 2, 2026Updated last week
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆556Sep 19, 2026Updated 3 weeks ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 10 months ago
- Using e-graphs for logic synthesis (ICCAD'25)☆37Aug 28, 2026Updated last month