ymherklotz / verismithLinks
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
☆110Updated 3 months ago
Alternatives and similar repositories for verismith
Users that are interested in verismith are comparing it to the libraries listed below
Sorting:
- ☆103Updated 3 years ago
- Hardware generator debugger☆75Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- ☆23Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- Equivalence checking with Yosys☆45Updated 2 weeks ago
- high-performance RTL simulator☆173Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- Mutation Cover with Yosys (MCY)☆85Updated 2 weeks ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- RISC-V Formal Verification Framework☆145Updated this week
- SystemVerilog frontend for Yosys☆151Updated last week
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- SystemVerilog synthesis tool☆208Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- FPGA tool performance profiling☆102Updated last year
- ☆56Updated 3 years ago
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- Next generation CGRA generator☆113Updated 2 weeks ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆49Updated 4 months ago
- Main page☆126Updated 5 years ago
- A SystemVerilog source file pickler.☆59Updated 10 months ago