ymherklotz / verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
☆99Updated 3 months ago
Alternatives and similar repositories for verismith:
Users that are interested in verismith are comparing it to the libraries listed below
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆99Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆81Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- Main page☆125Updated 5 years ago
- ☆102Updated 2 years ago
- Next generation CGRA generator☆109Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆119Updated 8 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆139Updated 2 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- RISC-V Formal Verification Framework☆127Updated last month
- high-performance RTL simulator☆152Updated 8 months ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆23Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- Hardware generator debugger☆73Updated last year
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- ☆54Updated 2 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆132Updated 4 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- SystemVerilog frontend for Yosys☆74Updated this week
- A SystemVerilog source file pickler.☆54Updated 4 months ago
- An automatic clock gating utility☆43Updated 7 months ago
- A dynamic verification library for Chisel.☆146Updated 3 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago