abs-tudelft / vhsnunzipView external linksLinks
Hardware Snappy decompressor
☆11Sep 11, 2024Updated last year
Alternatives and similar repositories for vhsnunzip
Users that are interested in vhsnunzip are comparing it to the libraries listed below
Sorting:
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated last month
- AFU framework for streaming applications with CAPI.☆13Mar 5, 2018Updated 7 years ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆23Oct 29, 2025Updated 3 months ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- Verilog modules for software-defined radio.☆18Dec 31, 2012Updated 13 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated last year
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆63Nov 7, 2025Updated 3 months ago
- High-througput logic analyzer for FPGA☆16Oct 8, 2020Updated 5 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- ☆33Apr 30, 2023Updated 2 years ago
- The official repository of the local FPGA Development Kit.☆19Apr 30, 2019Updated 6 years ago
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Dec 7, 2017Updated 8 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated last year
- VHDL plugin for RgGen☆15Jan 7, 2026Updated last month
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Sep 22, 2025Updated 4 months ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 10 years ago
- Absolute encoder VHDL core☆20Feb 3, 2017Updated 9 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Aug 5, 2020Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆75Aug 29, 2024Updated last year
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- spi memory controller☆22Jan 5, 2017Updated 9 years ago
- ☆25Apr 4, 2025Updated 10 months ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- A "Hello World" for the Power8 CAPI Interface. Includes application C and RTL code.☆18Jul 10, 2015Updated 10 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Sep 16, 2025Updated 4 months ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- Streaming based VHDL parser.☆84Jul 15, 2024Updated last year
- Fletcher: A framework to integrate FPGA accelerators with Apache Arrow☆228Aug 11, 2025Updated 6 months ago