chipsalliance / caliptra-ssLinks
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
☆34Updated this week
Alternatives and similar repositories for caliptra-ss
Users that are interested in caliptra-ss are comparing it to the libraries listed below
Sorting:
- ☆32Updated last month
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- ☆20Updated this week
- ☆22Updated 6 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆16Updated last month
- APB UVC ported to Verilator☆11Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- CORE-V MCU UVM Environment and Test Bench☆25Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆17Updated 7 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- ☆28Updated 6 years ago
- ☆14Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- ☆25Updated 3 weeks ago
- Platform Level Interrupt Controller☆43Updated last year
- ☆29Updated last year
- APB Logic☆22Updated last month
- ☆10Updated 3 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last week
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago