aicodix / ira

Related projects ⓘ

Alternatives and complementary repositories for ira

• gnuradio / gr-verilog
  ☆15Updated last year
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆20Updated last month
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated last year
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• Victoromoniyi / gr-litex
  LiteX Accelerator Block for GNU Radio
  ☆24Updated 2 years ago
• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆16Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆53Updated last year
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆49Updated this week
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆55Updated 5 months ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆11Updated 2 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆20Updated last year
• pothosware / PothosZynq
  DMA source and sink blocks for Xilinx Zynq FPGAs
  ☆22Updated 4 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆44Updated last year
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 3 years ago
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 4 years ago
• B0WEN-HU / gr-verilog
  This is an OOT module for GNU Radio integrating verilog simulation feature
  ☆37Updated 5 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated 3 months ago
• yrrapt / caravel_amsat_txrx_ic
  ☆29Updated 3 years ago
• codyps / wimax_ofdm
  Partial Verilog implimentation of a WiMAX OFDM Phy
  ☆17Updated 12 years ago
• EttusResearch / rfnoc-pfb-channelizer
  RFNoC out-of-tree module for a channelizer
  ☆15Updated 6 years ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆25Updated this week
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆15Updated 5 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆26Updated 4 years ago
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆24Updated 10 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• suoto / fpga_cores
  ☆32Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆30Updated last month
• analogdevicesinc / HighSpeedConverterToolbox
  MATLAB toolbox for ADI high speed converter products
  ☆18Updated 2 weeks ago