aicodix / ira
SISO vector decoder for IRA-LDPC codes in VHDL
☆11Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for ira
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated last year
- LiteX Accelerator Block for GNU Radio☆24Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- DMA source and sink blocks for Xilinx Zynq FPGAs☆22Updated 4 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆21Updated last month
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆54Updated last year
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆87Updated 5 months ago
- DVB-S2 LDPC Decoder☆25Updated 10 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆37Updated 5 years ago
- ☆26Updated 7 years ago
- Wi-Fi LDPC codec Verilog IP core☆15Updated 5 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆12Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- OscillatorIMP ecosystem FPGA IP sources☆25Updated 2 weeks ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- Lime Adaptive Digital Predistortion☆23Updated 11 months ago
- ☆22Updated 8 years ago
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆18Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- ☆15Updated last year
- The implementation of AD9371 on KC705☆20Updated 4 years ago
- The source codes of the fast x86 LDPC decoder published☆25Updated 4 years ago
- RFNoC out-of-tree module for a channelizer☆15Updated 6 years ago
- pynq framework for antsdr☆33Updated 5 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆12Updated 5 years ago