Alternatives and similar repositories for ira

Users that are interested in ira are comparing it to the libraries listed below

• Victoromoniyi / gr-litex
  LiteX Accelerator Block for GNU Radio
  ☆24Updated 3 years ago
• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆17Updated 2 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆28Updated 2 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆14Updated 2 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 8 months ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• marsiau / PYNQ-RTL-SDR
  A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR
  ☆21Updated 5 years ago
• FDU-ME-ARC / NVMeCHA
  ☆15Updated 3 years ago
• EttusResearch / rfnoc-pfb-channelizer
  RFNoC out-of-tree module for a channelizer
  ☆16Updated 7 years ago
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated 2 years ago
• B0WEN-HU / gr-verilog
  This is an OOT module for GNU Radio integrating verilog simulation feature
  ☆38Updated 5 years ago
• gnuradio / gr-verilog
  ☆17Updated 2 years ago
• blegal / Fast_LDPC_decoder_for_ARM15
  LDPC decoders for ARM processor
  ☆11Updated 3 years ago
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆27Updated 10 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 6 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆54Updated last year
• Xilinx / RFNoC-HLS-ATSC-RX
  ☆27Updated 7 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆22Updated 3 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• mwrnd / innova2_xcku15p_ddr4_bram_gpio
  XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
  ☆18Updated last year
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 4 years ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆28Updated 2 months ago
• codyps / wimax_ofdm
  Partial Verilog implimentation of a WiMAX OFDM Phy
  ☆19Updated 13 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago