zeroasiccorp / ebrick-demoLinks
Demo: how to create a custom EBRICK
☆25Updated last year
Alternatives and similar repositories for ebrick-demo
Users that are interested in ebrick-demo are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Universal Memory Interface (UMI)☆157Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- ☆58Updated 10 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆80Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- ☆51Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago
- ☆33Updated last year
- Announcements related to Verilator☆44Updated 3 months ago
- Fabric generator and CAD tools.☆217Updated this week
- ☆86Updated 3 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated last week
- Structural Netlist API (and more) for EDA post synthesis flow development☆134Updated this week
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆91Updated last week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- WAL enables programmable waveform analysis.☆164Updated 3 months ago
- RISC-V Nox core☆71Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- An automatic clock gating utility☆52Updated 9 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- ☆91Updated 4 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- FuseSoC standard core library☆153Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last week