Alternatives and similar repositories for ebrick-demo:

Users that are interested in ebrick-demo are comparing it to the libraries listed below

• efabless / caravel_user_project_analog
  ☆45Updated 2 weeks ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆81Updated last week
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆143Updated this week
• efabless / mpw_precheck
  ☆36Updated 2 weeks ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆34Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• The-OpenROAD-Project / megaboom
  ☆24Updated 3 weeks ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆74Updated 3 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated 2 months ago
• vmunoz82 / sudoku-challenge
  Solving Sudokus using open source formal verification tools
  ☆16Updated 2 years ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆30Updated 11 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆37Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆33Updated 4 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆48Updated 2 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 5 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆39Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 9 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆63Updated 2 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• chipsalliance / fpga-interchange-schema
  ☆54Updated 2 years ago